Do not set PLLSAI dividers in LTDC code

[ProfFan]

For example:

embassy/embassy-stm32/src/ltdc.rs

Lines 52 to 65 in b0172bb

	stm32_metapac::RCC
	.dckcfgr1()
	.modify(|w| w.set_pllsaidivr(stm32_metapac::rcc::vals::Pllsaidivr::DIV2));
	// It is set to RCC_PLLSAIDIVR_2 in ST's BSP example for the STM32469I-DISCO.
	#[cfg(not(any(stm32f7, stm32u5)))]
	stm32_metapac::RCC
	.dckcfgr()
	.modify(|w| w.set_pllsaidivr(stm32_metapac::rcc::vals::Pllsaidivr::DIV2));
	});
	rcc::enable_and_reset::<T>();
	//new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh));

These depend on how we configure the RCC. Instead the documentation should say what clocks are required to be configured at RCC start, and how to set RDiv manually to get desired LTDC clock