-
Notifications
You must be signed in to change notification settings - Fork 1
/
bcc_s6_pg2.sch
3220 lines (3220 loc) · 64.3 KB
/
bcc_s6_pg2.sch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
v 20110115 2
C 1000 1000 0 0 0 EMBEDDEDtitle-bordered-C.sym
[
T 22000 17900 15 8 1 0 0 4 1
11
T 20000 17900 15 8 1 0 0 4 1
10
T 18000 17900 15 8 1 0 0 4 1
9
T 16000 17900 15 8 1 0 0 4 1
8
T 14000 17900 15 8 1 0 0 4 1
7
T 12000 17900 15 8 1 0 0 4 1
6
T 10000 17900 15 8 1 0 0 4 1
5
T 8000 17900 15 8 1 0 0 4 1
4
T 6000 17900 15 8 1 0 0 4 1
3
T 4000 17900 15 8 1 0 0 4 1
2
T 2000 17900 15 8 1 0 0 4 1
1
L 21000 18000 21000 17800 15 0 0 0 -1 -1
L 19000 18000 19000 17800 15 0 0 0 -1 -1
L 17000 18000 17000 17800 15 0 0 0 -1 -1
L 15000 18000 15000 17800 15 0 0 0 -1 -1
L 13000 18000 13000 17800 15 0 0 0 -1 -1
L 11000 18000 11000 17800 15 0 0 0 -1 -1
L 9000 18000 9000 17800 15 0 0 0 -1 -1
L 7000 18000 7000 17800 15 0 0 0 -1 -1
L 5000 18000 5000 17800 15 0 0 0 -1 -1
L 3000 18000 3000 17800 15 0 0 0 -1 -1
T 18000 1100 15 8 1 0 0 4 1
9
T 20000 1100 15 8 1 0 0 4 1
10
T 22000 1100 15 8 1 0 0 4 1
11
L 19000 1200 19000 1000 15 0 0 0 -1 -1
L 21000 1200 21000 1000 15 0 0 0 -1 -1
T 22900 2000 15 8 1 0 0 4 1
A
T 22900 4000 15 8 1 0 0 4 1
B
T 22900 6000 15 8 1 0 0 4 1
C
T 22900 8000 15 8 1 0 0 4 1
D
T 22900 10000 15 8 1 0 0 4 1
E
T 22900 12000 15 8 1 0 0 4 1
F
T 22900 14000 15 8 1 0 0 4 1
G
T 22900 16000 15 8 1 0 0 4 1
H
T 22900 17500 15 8 1 0 0 4 1
I
L 23000 3000 22800 3000 15 0 0 0 -1 -1
L 23000 5000 22800 5000 15 0 0 0 -1 -1
L 23000 7000 22800 7000 15 0 0 0 -1 -1
L 23000 9000 22800 9000 15 0 0 0 -1 -1
L 23000 11000 22800 11000 15 0 0 0 -1 -1
L 23000 13000 22800 13000 15 0 0 0 -1 -1
L 23000 15000 22800 15000 15 0 0 0 -1 -1
L 23000 17000 22800 17000 15 0 0 0 -1 -1
T 1100 17500 15 8 1 0 0 4 1
I
T 1100 16000 15 8 1 0 0 4 1
H
T 1100 14000 15 8 1 0 0 4 1
G
T 1100 12000 15 8 1 0 0 4 1
F
L 1200 17000 1000 17000 15 0 0 0 -1 -1
L 1200 15000 1000 15000 15 0 0 0 -1 -1
L 1200 13000 1000 13000 15 0 0 0 -1 -1
T 16000 1100 15 8 1 0 0 4 1
8
T 14000 1100 15 8 1 0 0 4 1
7
T 12000 1100 15 8 1 0 0 4 1
6
T 10000 1100 15 8 1 0 0 4 1
5
T 8000 1100 15 8 1 0 0 4 1
4
T 6000 1100 15 8 1 0 0 4 1
3
T 4000 1100 15 8 1 0 0 4 1
2
T 2000 1100 15 8 1 0 0 4 1
1
T 1100 2000 15 8 1 0 0 4 1
A
T 1100 4000 15 8 1 0 0 4 1
B
T 1100 6000 15 8 1 0 0 4 1
C
T 1100 8000 15 8 1 0 0 4 1
D
T 1100 10000 15 8 1 0 0 4 1
E
B 1200 1200 21600 16600 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 17000 1200 17000 1000 15 0 0 0 -1 -1
L 15000 1200 15000 1000 15 0 0 0 -1 -1
L 13000 1200 13000 1000 15 0 0 0 -1 -1
L 11000 1200 11000 1000 15 0 0 0 -1 -1
L 9000 1200 9000 1000 15 0 0 0 -1 -1
L 7000 1200 7000 1000 15 0 0 0 -1 -1
L 5000 1200 5000 1000 15 0 0 0 -1 -1
L 3000 1200 3000 1000 15 0 0 0 -1 -1
L 1200 3000 1000 3000 15 0 0 0 -1 -1
L 1200 5000 1000 5000 15 0 0 0 -1 -1
L 1200 7000 1000 7000 15 0 0 0 -1 -1
L 1200 9000 1000 9000 15 0 0 0 -1 -1
L 1200 11000 1000 11000 15 0 0 0 -1 -1
L 15200 1800 22800 1800 15 0 0 0 -1 -1
B 15200 1200 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 15300 1900 15 8 1 0 0 0 1
TITLE
T 17000 1300 15 8 1 0 0 0 1
OF
T 15300 1300 15 8 1 0 0 0 1
PAGE
T 18800 1300 15 8 1 0 0 0 1
DRAWN BY:
T 18800 1600 15 8 1 0 0 0 1
REVISION:
T 15300 1600 15 8 1 0 0 0 1
FILE:
L 18700 1800 18700 1200 15 0 0 0 -1 -1
T 15400 2500 5 10 0 0 0 0 1
graphical=1
B 1000 1000 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
]
{
T 15900 1600 5 10 1 1 0 0 1
file=bcc_s6_pg2.sch
T 19900 1300 5 10 1 1 0 0 1
author=Eric Brombaugh
}
C 2700 2000 1 0 0 EMBEDDEDmount_hole.sym
[
T 3495 1999 8 10 0 1 0 0 1
refdes=MH?
V 3599 2499 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
{
T 3599 2499 5 10 0 1 0 0 1
footprint=mount_hole
}
P 2700 2500 3300 2500 1 0 0
{
T 2700 2500 5 10 0 0 0 0 1
pintype=unknown
T 3355 2495 5 10 0 1 0 0 1
pinlabel=unknown
T 3205 2545 5 10 0 1 0 6 1
pinnumber=1
T 2700 2500 5 10 0 0 0 0 1
pinseq=1
T 3100 2800 5 10 0 1 0 0 1
device=mount_hole
}
]
{
T 3495 1999 5 10 1 1 0 0 1
refdes=MH2
T 2700 2000 5 10 0 0 0 0 1
footprint=mount_hole_125
}
C 2700 1300 1 0 0 EMBEDDEDmount_hole.sym
[
T 3495 1299 8 10 0 1 0 0 1
refdes=MH?
V 3599 1799 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
{
T 3599 1799 5 10 0 1 0 0 1
footprint=mount_hole
}
P 2700 1800 3300 1800 1 0 0
{
T 2700 1800 5 10 0 0 0 0 1
pintype=unknown
T 3355 1795 5 10 0 1 0 0 1
pinlabel=unknown
T 3205 1845 5 10 0 1 0 6 1
pinnumber=1
T 2700 1800 5 10 0 0 0 0 1
pinseq=1
T 3100 2100 5 10 0 1 0 0 1
device=mount_hole
}
]
{
T 3495 1299 5 10 1 1 0 0 1
refdes=MH4
T 2700 1300 5 10 0 0 0 0 1
footprint=mount_hole_125
}
C 1400 2000 1 0 0 EMBEDDEDmount_hole.sym
[
T 2195 1999 8 10 0 1 0 0 1
refdes=MH?
V 2299 2499 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
{
T 2299 2499 5 10 0 1 0 0 1
footprint=mount_hole
}
P 1400 2500 2000 2500 1 0 0
{
T 1400 2500 5 10 0 0 0 0 1
pintype=unknown
T 2055 2495 5 10 0 1 0 0 1
pinlabel=unknown
T 1905 2545 5 10 0 1 0 6 1
pinnumber=1
T 1400 2500 5 10 0 0 0 0 1
pinseq=1
T 1800 2800 5 10 0 1 0 0 1
device=mount_hole
}
]
{
T 2195 1999 5 10 1 1 0 0 1
refdes=MH1
T 1400 2000 5 10 0 0 0 0 1
footprint=mount_hole_125
}
C 1400 1300 1 0 0 EMBEDDEDmount_hole.sym
[
T 2195 1299 8 10 0 1 0 0 1
refdes=MH?
V 2299 1799 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
{
T 2299 1799 5 10 0 1 0 0 1
footprint=mount_hole
}
P 1400 1800 2000 1800 1 0 0
{
T 1400 1800 5 10 0 0 0 0 1
pintype=unknown
T 2055 1795 5 10 0 1 0 0 1
pinlabel=unknown
T 1905 1845 5 10 0 1 0 6 1
pinnumber=1
T 1400 1800 5 10 0 0 0 0 1
pinseq=1
T 1800 2100 5 10 0 1 0 0 1
device=mount_hole
}
]
{
T 2195 1299 5 10 1 1 0 0 1
refdes=MH3
T 1400 1300 5 10 0 0 0 0 1
footprint=mount_hole_125
}
T 19900 1600 9 10 1 0 0 0 1
-
T 15900 1300 9 10 1 0 0 0 1
2
T 17400 1300 9 10 1 0 0 0 1
3
T 15900 2000 9 10 1 0 0 0 1
Blank Canvas Cape S6 V0.1: Config, Clock & I/O Interface
C 3000 14300 1 0 0 EMBEDDED3.3V-plus-1.sym
[
T 3075 14550 9 8 1 0 0 0 1
+3.3V
T 3300 14300 8 8 0 0 0 0 1
net=+3.3V:1
P 3200 14300 3200 14500 1 0 0
{
T 3250 14350 5 6 0 1 0 0 1
pinnumber=1
T 3250 14350 5 6 0 0 0 0 1
pinseq=1
T 3250 14350 5 6 0 1 0 0 1
pinlabel=1
T 3250 14350 5 6 0 1 0 0 1
pintype=pwr
}
L 3050 14500 3350 14500 3 0 0 0 -1 -1
]
C 8300 13600 1 0 0 EMBEDDEDoutput-1.sym
[
T 8400 13900 5 10 0 0 0 0 1
device=OUTPUT
P 8300 13700 8500 13700 1 0 0
{
T 8550 13650 5 6 0 1 0 0 1
pinnumber=1
T 8550 13650 5 6 0 0 0 0 1
pinseq=1
}
L 8500 13800 8500 13600 3 0 0 0 -1 -1
L 8500 13800 9000 13800 3 0 0 0 -1 -1
L 9000 13800 9100 13700 3 0 0 0 -1 -1
L 9100 13700 9000 13600 3 0 0 0 -1 -1
L 9000 13600 8500 13600 3 0 0 0 -1 -1
]
{
T 8400 13900 5 10 0 0 0 0 1
device=OUTPUT
T 9200 13600 5 10 1 1 0 0 1
value=FPGA_INIT
T 8300 13600 5 10 0 1 180 0 1
net=FPGA_INIT:1
}
C 3200 15500 1 0 0 EMBEDDEDfxo-hc73.sym
[
P 4800 15600 4500 15600 1 0 0
{
T 4800 15600 5 8 0 0 0 0 1
pintype=pas
T 4445 15595 5 8 1 1 0 6 1
pinlabel=out
T 4595 15645 5 8 1 1 0 0 1
pinnumber=3
T 4800 15600 5 8 0 0 0 0 1
pinseq=3
}
P 4500 15900 4800 15900 1 0 1
{
T 4595 15945 5 8 1 1 0 0 1
pinnumber=4
T 3950 15850 5 8 0 0 0 0 1
pinseq=4
T 4445 15895 5 8 1 1 0 6 1
pinlabel=vdd
T 3950 15850 5 8 0 1 0 0 1
pintype=pas
}
T 3500 16100 8 10 0 1 0 0 1
refdes=U?
B 3500 15500 1000 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 3500 15900 3200 15900 1 0 1
{
T 3405 15945 5 8 1 1 0 6 1
pinnumber=1
T 4050 15850 5 8 0 0 0 6 1
pinseq=1
T 3555 15895 5 8 1 1 0 0 1
pinlabel=ena
T 4050 15850 5 8 0 1 0 6 1
pintype=pas
}
P 3500 15600 3200 15600 1 0 1
{
T 3405 15645 5 8 1 1 0 6 1
pinnumber=2
T 4050 15550 5 8 0 0 0 6 1
pinseq=2
T 3555 15595 5 8 1 1 0 0 1
pinlabel=gnd
T 4050 15550 5 8 0 1 0 6 1
pintype=pas
}
T 1500 14000 5 10 0 0 0 0 1
device=fxo-hc73
]
{
T 3400 15200 5 10 1 1 0 0 1
device=VCC1-B3D-M50
T 3500 16100 5 10 1 1 0 0 1
refdes=U204
T 3200 15500 5 10 0 0 0 0 1
footprint=HC73
}
C 3000 13600 1 0 1 EMBEDDEDoutput-1.sym
[
L 2300 13600 2800 13600 3 0 0 0 -1 -1
L 2200 13700 2300 13600 3 0 0 0 -1 -1
L 2300 13800 2200 13700 3 0 0 0 -1 -1
L 2800 13800 2300 13800 3 0 0 0 -1 -1
L 2800 13800 2800 13600 3 0 0 0 -1 -1
P 3000 13700 2800 13700 1 0 0
{
T 2750 13650 5 6 0 0 0 6 1
pinseq=1
T 2750 13650 5 6 0 1 0 6 1
pinnumber=1
}
T 2900 13900 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 2900 13900 5 10 0 0 0 6 1
device=OUTPUT
T 2100 13600 5 10 1 1 0 6 1
value=I2C2_SDA
T 3000 13600 5 10 0 1 180 6 1
net=I2C2_SDA:1
}
C 3000 14000 1 0 1 EMBEDDEDoutput-1.sym
[
L 2300 14000 2800 14000 3 0 0 0 -1 -1
L 2200 14100 2300 14000 3 0 0 0 -1 -1
L 2300 14200 2200 14100 3 0 0 0 -1 -1
L 2800 14200 2300 14200 3 0 0 0 -1 -1
L 2800 14200 2800 14000 3 0 0 0 -1 -1
P 3000 14100 2800 14100 1 0 0
{
T 2750 14050 5 6 0 0 0 6 1
pinseq=1
T 2750 14050 5 6 0 1 0 6 1
pinnumber=1
}
T 2900 14300 5 10 0 0 0 6 1
device=OUTPUT
]
{
T 2900 14300 5 10 0 0 0 6 1
device=OUTPUT
T 2100 14000 5 10 1 1 0 6 1
value=I2C2_SCL
T 3000 14000 5 10 0 1 180 6 1
net=I2C2_SCL:1
}
N 3400 13700 3000 13700 4
N 3000 14100 3600 14100 4
N 8300 13700 6500 13700 4
N 8300 13500 6500 13500 4
N 6500 13100 8300 13100 4
C 2900 15300 1 0 0 EMBEDDEDgnd-1.sym
[
L 2980 15310 3020 15310 3 0 0 0 -1 -1
L 2955 15350 3045 15350 3 0 0 0 -1 -1
L 2900 15400 3100 15400 3 0 0 0 -1 -1
P 3000 15400 3000 15600 1 0 1
{
T 3058 15461 5 4 0 1 0 0 1
pinnumber=1
T 3058 15461 5 4 0 0 0 0 1
pinseq=1
T 3058 15461 5 4 0 1 0 0 1
pinlabel=1
T 3058 15461 5 4 0 1 0 0 1
pintype=pwr
}
T 3200 15350 8 10 0 0 0 0 1
net=GND:1
]
C 4700 16500 1 0 0 EMBEDDED3.3V-plus-1.sym
[
L 4750 16700 5050 16700 3 0 0 0 -1 -1
P 4900 16500 4900 16700 1 0 0
{
T 4950 16550 5 6 0 1 0 0 1
pinnumber=1
T 4950 16550 5 6 0 0 0 0 1
pinseq=1
T 4950 16550 5 6 0 1 0 0 1
pinlabel=1
T 4950 16550 5 6 0 1 0 0 1
pintype=pwr
}
T 5000 16500 8 8 0 0 0 0 1
net=+3.3V:1
T 4775 16750 9 8 1 0 0 0 1
+3.3V
]
N 4900 15900 4900 16500 4
N 3200 15600 3000 15600 4
N 4900 15900 4800 15900 4
N 3000 15900 3000 16400 4
N 3000 16400 4900 16400 4
N 3000 15900 3200 15900 4
N 4800 15600 8300 15600 4
C 8300 15500 1 0 0 EMBEDDEDoutput-1.sym
[
P 8300 15600 8500 15600 1 0 0
{
T 8550 15550 5 6 0 0 0 0 1
pinseq=1
T 8550 15550 5 6 0 1 0 0 1
pinnumber=1
}
L 8500 15700 8500 15500 3 0 0 0 -1 -1
L 8500 15700 9000 15700 3 0 0 0 -1 -1
L 9000 15700 9100 15600 3 0 0 0 -1 -1
L 9100 15600 9000 15500 3 0 0 0 -1 -1
L 9000 15500 8500 15500 3 0 0 0 -1 -1
T 8400 15800 5 10 0 0 0 0 1
device=OUTPUT
]
{
T 8400 15800 5 10 0 0 0 0 1
device=OUTPUT
T 9200 15500 5 10 1 1 0 0 1
value=FPGA_CLK50
T 8300 15500 5 10 0 1 180 0 1
net=FPGA_CLK50:1
}
C 3300 11500 1 0 0 EMBEDDEDgnd-1.sym
[
P 3400 11600 3400 11800 1 0 1
{
T 3458 11661 5 4 0 1 0 0 1
pintype=pwr
T 3458 11661 5 4 0 1 0 0 1
pinlabel=1
T 3458 11661 5 4 0 0 0 0 1
pinseq=1
T 3458 11661 5 4 0 1 0 0 1
pinnumber=1
}
L 3300 11600 3500 11600 3 0 0 0 -1 -1
L 3355 11550 3445 11550 3 0 0 0 -1 -1
L 3380 11510 3420 11510 3 0 0 0 -1 -1
T 3600 11550 8 10 0 0 0 0 1
net=GND:1
]
N 3300 12500 3800 12500 4
N 3100 12700 3800 12700 4
N 3400 12100 3800 12100 4
T 1400 11500 9 10 1 0 0 0 2
I2C Address Mapping
0 - 0x38
C 4900 16000 1 0 0 EMBEDDEDcapacitor-1.sym
[
P 4900 16200 5100 16200 1 0 0
{
T 5100 16200 5 8 0 1 0 2 1
pintype=pas
T 5100 16200 9 8 0 1 0 0 1
pinlabel=1
T 5050 16150 5 8 0 1 0 8 1
pinseq=1
T 5050 16250 5 8 0 1 0 6 1
pinnumber=1
}
P 5800 16200 5600 16200 1 0 0
{
T 5600 16200 5 8 0 1 0 8 1
pintype=pas
T 5600 16200 9 8 0 1 0 6 1
pinlabel=2
T 5650 16150 5 8 0 1 0 2 1
pinseq=2
T 5650 16250 5 8 0 1 0 0 1
pinnumber=2
}
L 5300 16400 5300 16000 3 0 0 0 -1 -1
L 5400 16400 5400 16000 3 0 0 0 -1 -1
L 5600 16200 5400 16200 3 0 0 0 -1 -1
L 5300 16200 5100 16200 3 0 0 0 -1 -1
T 5100 16700 5 10 0 0 0 0 1
device=CAPACITOR
T 5100 16500 8 10 0 1 0 0 1
refdes=C?
T 5100 17300 5 10 0 0 0 0 1
description=capacitor
T 5100 17100 5 10 0 0 0 0 1
numslots=0
T 5100 16900 5 10 0 0 0 0 1
symversion=0.1
]
{
T 5100 16700 5 10 0 0 0 0 1
device=CAPACITOR
T 5300 16400 5 10 1 1 0 0 1
value=0.1uf
T 4900 16000 5 10 0 0 270 0 1
footprint=my_0603
T 5300 16600 5 10 1 1 0 0 1
refdes=C202
}
C 5700 15900 1 0 0 EMBEDDEDgnd-1.sym
[
P 5800 16000 5800 16200 1 0 1
{
T 5858 16061 5 4 0 1 0 0 1
pintype=pwr
T 5858 16061 5 4 0 1 0 0 1
pinlabel=1
T 5858 16061 5 4 0 0 0 0 1
pinseq=1
T 5858 16061 5 4 0 1 0 0 1
pinnumber=1
}
L 5700 16000 5900 16000 3 0 0 0 -1 -1
L 5755 15950 5845 15950 3 0 0 0 -1 -1
L 5780 15910 5820 15910 3 0 0 0 -1 -1
T 6000 15950 8 10 0 0 0 0 1
net=GND:1
]
C 2900 12700 1 0 1 EMBEDDEDcapacitor-1.sym
[
L 2500 12900 2700 12900 3 0 0 0 -1 -1
L 2200 12900 2400 12900 3 0 0 0 -1 -1
L 2400 13100 2400 12700 3 0 0 0 -1 -1
L 2500 13100 2500 12700 3 0 0 0 -1 -1
P 2000 12900 2200 12900 1 0 0
{
T 2150 12950 5 8 0 1 0 6 1
pinnumber=2
T 2150 12850 5 8 0 1 0 8 1
pinseq=2
T 2200 12900 9 8 0 1 0 0 1
pinlabel=2
T 2200 12900 5 8 0 1 0 2 1
pintype=pas
}
P 2900 12900 2700 12900 1 0 0
{
T 2750 12950 5 8 0 1 0 0 1
pinnumber=1
T 2750 12850 5 8 0 1 0 2 1
pinseq=1
T 2700 12900 9 8 0 1 0 6 1
pinlabel=1
T 2700 12900 5 8 0 1 0 8 1
pintype=pas
}
T 2700 13600 5 10 0 0 0 6 1
symversion=0.1
T 2700 13800 5 10 0 0 0 6 1
numslots=0
T 2700 14000 5 10 0 0 0 6 1
description=capacitor
T 2700 13200 8 10 0 1 0 6 1
refdes=C?
T 2700 13400 5 10 0 0 0 6 1
device=CAPACITOR
]
{
T 2700 13400 5 10 0 0 0 6 1
device=CAPACITOR
T 2100 13400 5 10 1 1 180 6 1
refdes=C201
T 2500 13100 5 10 1 1 0 6 1
value=0.1uf
T 2900 12700 5 10 0 0 270 2 1
footprint=my_0603
}
C 2100 12600 1 0 1 EMBEDDEDgnd-1.sym
[
L 2020 12610 1980 12610 3 0 0 0 -1 -1
L 2045 12650 1955 12650 3 0 0 0 -1 -1
L 2100 12700 1900 12700 3 0 0 0 -1 -1
P 2000 12700 2000 12900 1 0 1
{
T 1942 12761 5 4 0 1 0 6 1
pinnumber=1
T 1942 12761 5 4 0 0 0 6 1
pinseq=1
T 1942 12761 5 4 0 1 0 6 1
pinlabel=1
T 1942 12761 5 4 0 1 0 6 1
pintype=pwr
}
T 1800 12650 8 10 0 0 0 6 1
net=GND:1
]
N 17200 11600 17200 16400 4
N 17600 12600 17200 12600 4
N 19400 11600 19400 16400 4
N 19400 11600 17200 11600 4
N 19000 12600 19400 12600 4
N 16800 12300 16800 12400 4
N 19300 12800 19000 12800 4
N 17300 12800 17600 12800 4
C 19900 15900 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 16200 5 10 0 0 0 0 1
device=OUTPUT
L 20600 15900 20100 15900 3 0 0 0 -1 -1
L 20700 16000 20600 15900 3 0 0 0 -1 -1
L 20600 16100 20700 16000 3 0 0 0 -1 -1
L 20100 16100 20600 16100 3 0 0 0 -1 -1
L 20100 16100 20100 15900 3 0 0 0 -1 -1
P 19900 16000 20100 16000 1 0 0
{
T 20150 15950 5 6 0 1 0 0 1
pinnumber=1
T 20150 15950 5 6 0 0 0 0 1
pinseq=1
}
]
{
T 20000 16200 5 10 0 0 0 0 1
device=OUTPUT
T 20800 15900 5 10 1 1 0 0 1
value=JA4
T 19900 15900 5 10 0 1 180 0 1
net=JA4:1
}
C 19900 15700 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 16000 5 10 0 0 0 0 1
device=OUTPUT
P 19900 15800 20100 15800 1 0 0
{
T 20150 15750 5 6 0 0 0 0 1
pinseq=1
T 20150 15750 5 6 0 1 0 0 1
pinnumber=1
}
L 20100 15900 20100 15700 3 0 0 0 -1 -1
L 20100 15900 20600 15900 3 0 0 0 -1 -1
L 20600 15900 20700 15800 3 0 0 0 -1 -1
L 20700 15800 20600 15700 3 0 0 0 -1 -1
L 20600 15700 20100 15700 3 0 0 0 -1 -1
]
{
T 20000 16000 5 10 0 0 0 0 1
device=OUTPUT
T 20800 15700 5 10 1 1 0 0 1
value=JA5
T 19900 15700 5 10 0 1 180 0 1
net=JA5:1
}
C 19900 15500 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 15800 5 10 0 0 0 0 1
device=OUTPUT
P 19900 15600 20100 15600 1 0 0
{
T 20150 15550 5 6 0 0 0 0 1
pinseq=1
T 20150 15550 5 6 0 1 0 0 1
pinnumber=1
}
L 20100 15700 20100 15500 3 0 0 0 -1 -1
L 20100 15700 20600 15700 3 0 0 0 -1 -1
L 20600 15700 20700 15600 3 0 0 0 -1 -1
L 20700 15600 20600 15500 3 0 0 0 -1 -1
L 20600 15500 20100 15500 3 0 0 0 -1 -1
]
{
T 20000 15800 5 10 0 0 0 0 1
device=OUTPUT
T 20800 15500 5 10 1 1 0 0 1
value=JA6
T 19900 15500 5 10 0 1 180 0 1
net=JA6:1
}
C 19900 15300 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 15600 5 10 0 0 0 0 1
device=OUTPUT
P 19900 15400 20100 15400 1 0 0
{
T 20150 15350 5 6 0 0 0 0 1
pinseq=1
T 20150 15350 5 6 0 1 0 0 1
pinnumber=1
}
L 20100 15500 20100 15300 3 0 0 0 -1 -1
L 20100 15500 20600 15500 3 0 0 0 -1 -1
L 20600 15500 20700 15400 3 0 0 0 -1 -1
L 20700 15400 20600 15300 3 0 0 0 -1 -1
L 20600 15300 20100 15300 3 0 0 0 -1 -1
]
{
T 20000 15600 5 10 0 0 0 0 1
device=OUTPUT
T 20800 15300 5 10 1 1 0 0 1
value=JA7
T 19900 15300 5 10 0 1 180 0 1
net=JA7:1
}
C 19900 15100 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 15400 5 10 0 0 0 0 1
device=OUTPUT
P 19900 15200 20100 15200 1 0 0
{
T 20150 15150 5 6 0 0 0 0 1
pinseq=1
T 20150 15150 5 6 0 1 0 0 1
pinnumber=1
}
L 20100 15300 20100 15100 3 0 0 0 -1 -1
L 20100 15300 20600 15300 3 0 0 0 -1 -1
L 20600 15300 20700 15200 3 0 0 0 -1 -1
L 20700 15200 20600 15100 3 0 0 0 -1 -1
L 20600 15100 20100 15100 3 0 0 0 -1 -1
]
{
T 20000 15400 5 10 0 0 0 0 1
device=OUTPUT
T 20800 15100 5 10 1 1 0 0 1
value=JB4
T 19900 15100 5 10 0 1 180 0 1
net=JB4:1
}
C 19900 14900 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 15200 5 10 0 0 0 0 1
device=OUTPUT
L 20600 14900 20100 14900 3 0 0 0 -1 -1
L 20700 15000 20600 14900 3 0 0 0 -1 -1
L 20600 15100 20700 15000 3 0 0 0 -1 -1
L 20100 15100 20600 15100 3 0 0 0 -1 -1
L 20100 15100 20100 14900 3 0 0 0 -1 -1
P 19900 15000 20100 15000 1 0 0
{
T 20150 14950 5 6 0 1 0 0 1
pinnumber=1
T 20150 14950 5 6 0 0 0 0 1
pinseq=1
}
]
{
T 20000 15200 5 10 0 0 0 0 1
device=OUTPUT
T 20800 14900 5 10 1 1 0 0 1
value=JB5
T 19900 14900 5 10 0 1 180 0 1
net=JB5:1
}
C 19900 14700 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 15000 5 10 0 0 0 0 1
device=OUTPUT
L 20600 14700 20100 14700 3 0 0 0 -1 -1
L 20700 14800 20600 14700 3 0 0 0 -1 -1
L 20600 14900 20700 14800 3 0 0 0 -1 -1
L 20100 14900 20600 14900 3 0 0 0 -1 -1
L 20100 14900 20100 14700 3 0 0 0 -1 -1
P 19900 14800 20100 14800 1 0 0
{
T 20150 14750 5 6 0 1 0 0 1
pinnumber=1
T 20150 14750 5 6 0 0 0 0 1
pinseq=1
}
]
{
T 20000 15000 5 10 0 0 0 0 1
device=OUTPUT
T 20800 14700 5 10 1 1 0 0 1
value=JB6
T 19900 14700 5 10 0 1 180 0 1
net=JB6:1
}
C 19900 14500 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 14800 5 10 0 0 0 0 1
device=OUTPUT
L 20600 14500 20100 14500 3 0 0 0 -1 -1
L 20700 14600 20600 14500 3 0 0 0 -1 -1
L 20600 14700 20700 14600 3 0 0 0 -1 -1
L 20100 14700 20600 14700 3 0 0 0 -1 -1
L 20100 14700 20100 14500 3 0 0 0 -1 -1
P 19900 14600 20100 14600 1 0 0
{
T 20150 14550 5 6 0 1 0 0 1
pinnumber=1
T 20150 14550 5 6 0 0 0 0 1
pinseq=1
}
]
{
T 20000 14800 5 10 0 0 0 0 1
device=OUTPUT
T 20800 14500 5 10 1 1 0 0 1
value=JB7
T 19900 14500 5 10 0 1 180 0 1
net=JB7:1
}
C 19900 14300 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 14600 5 10 0 0 0 0 1
device=OUTPUT
P 19900 14400 20100 14400 1 0 0
{
T 20150 14350 5 6 0 0 0 0 1
pinseq=1
T 20150 14350 5 6 0 1 0 0 1
pinnumber=1
}
L 20100 14500 20100 14300 3 0 0 0 -1 -1
L 20100 14500 20600 14500 3 0 0 0 -1 -1
L 20600 14500 20700 14400 3 0 0 0 -1 -1
L 20700 14400 20600 14300 3 0 0 0 -1 -1
L 20600 14300 20100 14300 3 0 0 0 -1 -1
]
{
T 20000 14600 5 10 0 0 0 0 1
device=OUTPUT
T 20800 14300 5 10 1 1 0 0 1
value=JC4
T 19900 14300 5 10 0 1 180 0 1
net=JC4:1
}
C 19900 14100 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 14400 5 10 0 0 0 0 1
device=OUTPUT
L 20600 14100 20100 14100 3 0 0 0 -1 -1
L 20700 14200 20600 14100 3 0 0 0 -1 -1
L 20600 14300 20700 14200 3 0 0 0 -1 -1
L 20100 14300 20600 14300 3 0 0 0 -1 -1
L 20100 14300 20100 14100 3 0 0 0 -1 -1
P 19900 14200 20100 14200 1 0 0
{
T 20150 14150 5 6 0 1 0 0 1
pinnumber=1
T 20150 14150 5 6 0 0 0 0 1
pinseq=1
}
]
{
T 20000 14400 5 10 0 0 0 0 1
device=OUTPUT
T 20800 14100 5 10 1 1 0 0 1
value=JC5
T 19900 14100 5 10 0 1 180 0 1
net=JC5:1
}
C 19900 13900 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 14200 5 10 0 0 0 0 1
device=OUTPUT
L 20600 13900 20100 13900 3 0 0 0 -1 -1
L 20700 14000 20600 13900 3 0 0 0 -1 -1
L 20600 14100 20700 14000 3 0 0 0 -1 -1
L 20100 14100 20600 14100 3 0 0 0 -1 -1
L 20100 14100 20100 13900 3 0 0 0 -1 -1
P 19900 14000 20100 14000 1 0 0
{
T 20150 13950 5 6 0 1 0 0 1
pinnumber=1
T 20150 13950 5 6 0 0 0 0 1
pinseq=1
}
]
{
T 20000 14200 5 10 0 0 0 0 1
device=OUTPUT
T 20800 13900 5 10 1 1 0 0 1
value=JC6
T 19900 13900 5 10 0 1 180 0 1
net=JC6:1
}
C 19900 13700 1 0 0 EMBEDDEDoutput-1.sym
[
T 20000 14000 5 10 0 0 0 0 1
device=OUTPUT
L 20600 13700 20100 13700 3 0 0 0 -1 -1
L 20700 13800 20600 13700 3 0 0 0 -1 -1
L 20600 13900 20700 13800 3 0 0 0 -1 -1
L 20100 13900 20600 13900 3 0 0 0 -1 -1
L 20100 13900 20100 13700 3 0 0 0 -1 -1
P 19900 13800 20100 13800 1 0 0
{
T 20150 13750 5 6 0 1 0 0 1
pinnumber=1
T 20150 13750 5 6 0 0 0 0 1
pinseq=1
}
]
{
T 20000 14000 5 10 0 0 0 0 1
device=OUTPUT
T 20800 13700 5 10 1 1 0 0 1
value=JC7
T 19900 13700 5 10 0 1 180 0 1
net=JC7:1
}
C 16700 15900 1 0 1 EMBEDDEDoutput-1.sym
[
T 16600 16200 5 10 0 0 0 6 1
device=OUTPUT
P 16700 16000 16500 16000 1 0 0
{
T 16450 15950 5 6 0 0 0 6 1
pinseq=1
T 16450 15950 5 6 0 1 0 6 1
pinnumber=1
}
L 16500 16100 16500 15900 3 0 0 0 -1 -1
L 16500 16100 16000 16100 3 0 0 0 -1 -1
L 16000 16100 15900 16000 3 0 0 0 -1 -1
L 15900 16000 16000 15900 3 0 0 0 -1 -1
L 16000 15900 16500 15900 3 0 0 0 -1 -1
]
{
T 16600 16200 5 10 0 0 0 6 1
device=OUTPUT
T 15800 15900 5 10 1 1 0 6 1
value=JA0
T 16700 15900 5 10 0 1 180 6 1
net=JA0:1
}
C 16700 15700 1 0 1 EMBEDDEDoutput-1.sym
[
T 16600 16000 5 10 0 0 0 6 1
device=OUTPUT
L 16000 15700 16500 15700 3 0 0 0 -1 -1
L 15900 15800 16000 15700 3 0 0 0 -1 -1
L 16000 15900 15900 15800 3 0 0 0 -1 -1
L 16500 15900 16000 15900 3 0 0 0 -1 -1