WIP on Scc instructions

src/cpu/ops/handlers.rs

@@ -51,6 +51,7 @@ const OP_SUBQ  : u32 = 0b0101_0001_0000_0000;
 const OP_SUBX  : u32 = 0b1001_0001_0000_0000;
 const OP_SBCD  : u32 = 0b1000_0001_0000_0000;
 const OP_SWAP  : u32 = 0b0100_1000_0000_0000;
+const OP_SCC   : u32 = 0b0101_0000_1100_0000;
 
 const IF_T : u32 = 0b0000_0000_0000; // True            1
 const IF_F : u32 = 0b0001_0000_0000; // False           0
@@ -810,6 +811,15 @@ pub const OP_LEA_32_PCIX : u32 = OP_LEA | OPER_PCIX;
 pub const OP_SBCD_8_RR: u32 = OP_SBCD | BYTE_SIZED | RR_MODE;
 pub const OP_SBCD_8_MM: u32 = OP_SBCD | BYTE_SIZED | MM_MODE;
 
+pub const OP_SHI_8_AI      : u32 = OP_SCC | IF_HI | OPER_AI;
+pub const OP_SHI_8_AL      : u32 = OP_SCC | IF_HI | OPER_AL;
+pub const OP_SHI_8_AW      : u32 = OP_SCC | IF_HI | OPER_AW;
+pub const OP_SHI_8_DN      : u32 = OP_SCC | IF_HI | OPER_DN;
+pub const OP_SHI_8_DI      : u32 = OP_SCC | IF_HI | OPER_DI;
+pub const OP_SHI_8_IX      : u32 = OP_SCC | IF_HI | OPER_IX;
+pub const OP_SHI_8_PD      : u32 = OP_SCC | IF_HI | OPER_PD;
+pub const OP_SHI_8_PI      : u32 = OP_SCC | IF_HI | OPER_PI;
+
 // Put constants for Scc here
 // Put constants for STOP here
 // Put constants for SUB here
@@ -1667,6 +1677,19 @@ pub fn generate() -> InstructionSet {
         op_entry!(MASK_OUT_X_Y, OP_SBCD_8_RR, sbcd_8_rr),
         op_entry!(MASK_OUT_X_Y, OP_SBCD_8_MM, sbcd_8_mm),
 
+        /*
+        op_entry!(MASK_OUT_Y, OP_SHI_8_AI, shi_8_ai),
+        op_entry!(MASK_EXACT, OP_SHI_8_AL, shi_8_al),
+        op_entry!(MASK_EXACT, OP_SHI_8_AW, shi_8_aw),
+        */
+        op_entry!(MASK_OUT_X, OP_SHI_8_DN, shi_8_dn),
+        /*
+        op_entry!(MASK_OUT_Y, OP_SHI_8_DI, shi_8_di),
+        op_entry!(MASK_OUT_Y, OP_SHI_8_IX, shi_8_ix),
+        op_entry!(MASK_OUT_Y, OP_SHI_8_PD, shi_8_pd),
+        op_entry!(MASK_OUT_Y, OP_SHI_8_PI, shi_8_pi),
+        */
+
         // Put op-entries for Scc here
         // Put op-entries for STOP here
         // Put op-entries for SUB here

src/cpu/ops/mod.rs

@@ -1512,6 +1512,32 @@ lea!(lea_32_pcix, index_pc, 12);
 impl_op!(8, sbcd_8, sbcd_8_rr, dy, dx, 6);
 impl_op!(8, sbcd_8, sbcd_8_mm, ay_pd_8, ea_ax_pd_8, 18);
 
+macro_rules! shi_8 {
+    ($name:ident, $dst:ident, $write_op:ident, $cycles:expr) => (
+        pub fn $name(core: &mut Core) -> Result<Cycles> {
+            // The MC68000PRM says: In the MC68000 and MC68008 a memory location is read before it is cleared.
+            // We skip this as Musashi doesn't do that either.
+            let ea = try!(effective_address::$dst(core));
+
+            core.$write_op(ea, 0);
+
+            core.n_flag = 0;
+            core.v_flag = 0;
+            core.c_flag = 0;
+            core.not_z_flag = 0;
+            Ok(Cycles($cycles))
+        });
+}
+
+pub fn shi_8_dn(core: &mut Core) -> Result<Cycles> {
+    let t = match core.cond_hi()  {
+        false => 0u32,
+        true => 0xffu32,
+    };
+    dy!(core) = t;
+    Ok(Cycles(4))
+}
+
 // Put implementation of Scc ops here
 // Put implementation of STOP ops here
 // Put implementation of SUB ops here

src/musashi.rs

@@ -1205,6 +1205,19 @@ mod tests {
     qc8!(OP_SBCD_8_RR, qc_sbcd_rr);
     qc8!(OP_SBCD_8_MM, qc_sbcd_mm);
 
+    /*
+    qc8!(OP_SHI_8_AI, qc_shi_8_ai);
+    qc8!(OP_SHI_8_AL, qc_shi_8_al);
+    qc8!(OP_SHI_8_AW, qc_shi_8_aw);
+    */
+    qc!(OP_SHI_8_DN, qc_shi_8_dn);
+    /*
+    qc8!(OP_SHI_8_DI, qc_shi_8_di);
+    qc8!(OP_SHI_8_IX, qc_shi_8_ix);
+    qc8!(OP_SHI_8_PD, qc_shi_8_pd);
+    qc8!(OP_SHI_8_PI, qc_shi_8_pi);
+    */
+
     // Put qc for Scc here
     // Put qc for STOP here
     // Put qc for SUB here