Skip to content

Breaks Debugger 1.5
Compare
Choose a tag to compare
@ogamespec ogamespec released this 17 Jan 23:59
· 2266 commits to master since this release
breaks-debug-15
189e73c
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.

Fixed emulation of the S register.

The problem was on the penultimate half-cycle of the JSR instruction (T1 PHI1):

image

(Yes, the developers of the 6502 have been very creative in naming the cycles and so, for example, the sequence of JSRs is: T2, T3, T4, T5, T0, T1)

It would seem that the value from the ALU via the SB bus is stored in the S register and goes straight to the PCL register.

But we didn't take into account the special feature of the S register:

image

It has two latches, one for the input (for S/S and SB/S commands) and one for the output (for S/ADL and S/SB commands).

So what actually happens here is that it takes a new PCL value from the S output latch and loads the old S value from the ALU to the input latch.

Analyzing how the JSR instruction works, we can say that the low byte for the PCL is temporarily stored on the stack pointer and the ALU is used as temporary storage for the stack pointer.

This release is a confirmation that we are on the right track and the lower part will be debugged so that all other instructions work properly.

Assets 3