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dwc_otg_pcd.c
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dwc_otg_pcd.c
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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
* $Revision: #104 $
* $Date: 2012/12/21 $
* $Change: 2131568 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef DWC_HOST_ONLY
/** @file
* This file implements PCD Core. All code in this file is portable and doesn't
* use any OS specific functions.
* PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
* header file, which can be used to implement OS specific PCD interface.
*
* An important function of the PCD is managing interrupts generated
* by the DWC_otg controller. The implementation of the DWC_otg device
* mode interrupt service routines is in dwc_otg_pcd_intr.c.
*
* @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
* @todo Does it work when the request size is greater than DEPTSIZ
* transfer size
*
*/
#include "dwc_otg_pcd.h"
#ifdef DWC_UTE_CFI
#include "dwc_otg_cfi.h"
extern int init_cfi(cfiobject_t * cfiobj);
#endif
static const char * bc_name[]={
"UNKNOWN (Disconnect)",
"SDP (PC)",
"DCP (Charger)",
"CDP (PC with Charger)",
};
#define T_DCD_TIMEOUT 10
#define T_VDPSRC_ON 40
#define T_VDMSRC_EN (20 + 5)
#define T_VDMSRC_DIS (20 + 5)
#define T_VDMSRC_ON 40
int dwc_otg_charger_detect(dwc_otg_core_if_t * _core_if)
{
usb_peri_reg_t *peri;
usb_adp_bc_data_t adp_bc;
int bc_mode = USB_BC_MODE_DISCONNECT;
int timeout_det;
peri = _core_if->usb_peri_reg;
adp_bc.d32 = DWC_READ_REG32(&peri->adp_bc);
if(adp_bc.b.device_sess_vld){
DWC_MDELAY(T_DCD_TIMEOUT);
/* Turn on VDPSRC */
adp_bc.b.chrgsel = 0;
adp_bc.b.vdatdetenb = 1;
adp_bc.b.vdatsrcenb = 1;
adp_bc.b.dcd_enable = 0;
DWC_WRITE_REG32(&peri->adp_bc,adp_bc.d32);
/* SDP and CDP/DCP distinguish */
timeout_det = T_VDMSRC_EN;
while(timeout_det--){
adp_bc.d32 = DWC_READ_REG32(&peri->adp_bc);
if(adp_bc.b.chg_det)
break;
DWC_MDELAY(1);
};
if(adp_bc.b.chg_det){
/* Turn off VDPSRC */
adp_bc.d32 = DWC_READ_REG32(&peri->adp_bc);
adp_bc.b.vdatdetenb = 0;
adp_bc.b.vdatsrcenb = 0;
DWC_WRITE_REG32(&peri->adp_bc,adp_bc.d32);
/* Wait VDMSRC_DIS */
timeout_det = T_VDMSRC_DIS;
while(timeout_det--){
adp_bc.d32 = DWC_READ_REG32(&peri->adp_bc);
if(!adp_bc.b.chg_det)
break;
DWC_MDELAY(1);
};
if(timeout_det <= 0)
DWC_WARN("Time out for VDMSRC_DIS!");
/* Turn on VDMSRC */
adp_bc.d32 = DWC_READ_REG32(&peri->adp_bc);
adp_bc.b.chrgsel = 1;
adp_bc.b.vdatdetenb = 1;
adp_bc.b.vdatsrcenb = 1;
DWC_WRITE_REG32(&peri->adp_bc,adp_bc.d32);
DWC_MDELAY(T_VDMSRC_ON);
adp_bc.d32 = DWC_READ_REG32(&peri->adp_bc);
if(adp_bc.b.chg_det)
bc_mode = USB_BC_MODE_DCP;
else
bc_mode = USB_BC_MODE_CDP;
}
else{
bc_mode = USB_BC_MODE_SDP;
}
adp_bc.d32 = DWC_READ_REG32(&peri->adp_bc);
adp_bc.b.vdatdetenb = 0;
adp_bc.b.vdatsrcenb = 0;
adp_bc.b.dcd_enable = 0;
DWC_WRITE_REG32(&peri->adp_bc,adp_bc.d32);
}
DWC_PRINTF("detected battery charger type: %s\n",bc_name[bc_mode]);
return bc_mode;
}
/**
* Choose endpoint from ep arrays using usb_ep structure.
*/
static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
{
int i;
if (pcd->ep0.priv == handle) {
return &pcd->ep0;
}
for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
if (pcd->in_ep[i].priv == handle)
return &pcd->in_ep[i];
if (pcd->out_ep[i].priv == handle)
return &pcd->out_ep[i];
}
return NULL;
}
/**
* This function completes a request. It call's the request call back.
*/
void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
int32_t status)
{
unsigned stopped = ep->stopped;
DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
/* don't modify queue heads during completion callback */
ep->stopped = 1;
/* spin_unlock/spin_lock now done in fops->complete() */
ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
req->actual);
if (ep->pcd->request_pending > 0) {
--ep->pcd->request_pending;
}
ep->stopped = stopped;
DWC_FREE(req);
}
/**
* This function terminates all the requsts in the EP request queue.
*/
void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
{
dwc_otg_pcd_request_t *req;
ep->stopped = 1;
/* called with irqs blocked?? */
while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
req = DWC_CIRCLEQ_FIRST(&ep->queue);
dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
}
}
void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
const struct dwc_otg_pcd_function_ops *fops)
{
pcd->fops = fops;
}
/**
* PCD Callback function for initializing the PCD when switching to
* device mode.
*
* @param p void pointer to the <code>dwc_otg_pcd_t</code>
*/
static int32_t dwc_otg_pcd_start_cb(void *p)
{
dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
/*
* Initialized the Core for Device mode.
*/
if (dwc_otg_is_device_mode(core_if)) {
dwc_otg_core_dev_init(core_if);
/* Set core_if's lock pointer to the pcd->lock */
core_if->lock = pcd->lock;
}
dwc_otg_set_vbus_power(core_if, 0);
return 1;
}
/** CFI-specific buffer allocation function for EP */
#ifdef DWC_UTE_CFI
uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
size_t buflen, int flags)
{
dwc_otg_pcd_ep_t *ep;
ep = get_ep_from_handle(pcd, pep);
if (!ep) {
DWC_WARN("bad ep\n");
return -DWC_E_INVALID;
}
return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
flags);
}
#else
uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
size_t buflen, int flags);
#endif
/**
* PCD Callback function for notifying the PCD when resuming from
* suspend.
*
* @param p void pointer to the <code>dwc_otg_pcd_t</code>
*/
static int32_t dwc_otg_pcd_resume_cb(void *p)
{
dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
if (pcd->fops->resume) {
pcd->fops->resume(pcd);
}
/* Stop the SRP timeout timer. */
if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
|| (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
if (GET_CORE_IF(pcd)->srp_timer_started) {
GET_CORE_IF(pcd)->srp_timer_started = 0;
DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
}
}
return 1;
}
/**
* PCD Callback function for notifying the PCD device is suspended.
*
* @param p void pointer to the <code>dwc_otg_pcd_t</code>
*/
static int32_t dwc_otg_pcd_suspend_cb(void *p)
{
dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
if (pcd->fops->suspend) {
/*
* To avoid deadlock in ISR code,
* temporarily remove these unlock/lock
*/
//DWC_SPINUNLOCK(pcd->lock);
pcd->fops->suspend(pcd);
//DWC_SPINLOCK(pcd->lock);
}
return 1;
}
/**
* PCD Callback function for stopping the PCD when switching to Host
* mode.
*
* @param p void pointer to the <code>dwc_otg_pcd_t</code>
*/
static int32_t dwc_otg_pcd_stop_cb(void *p)
{
dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
dwc_otg_pcd_stop(pcd);
return 1;
}
/**
* PCD Callback structure for handling mode switching.
*/
static dwc_otg_cil_callbacks_t pcd_callbacks = {
.start = dwc_otg_pcd_start_cb,
.stop = dwc_otg_pcd_stop_cb,
.suspend = dwc_otg_pcd_suspend_cb,
.resume_wakeup = dwc_otg_pcd_resume_cb,
};
/**
* This function allocates a DMA Descriptor chain for the Endpoint
* buffer to be used for a transfer to/from the specified endpoint.
*/
dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
uint32_t count)
{
return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t),
dma_desc_addr);
}
/**
* This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
*/
void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
uint32_t dma_desc_addr, uint32_t count)
{
DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
dma_desc_addr);
}
#ifdef DWC_EN_ISOC
/**
* This function initializes a descriptor chain for Isochronous transfer
*
* @param core_if Programming view of DWC_otg controller.
* @param dwc_ep The EP to start the transfer on.
*
*/
void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
dwc_ep_t * dwc_ep)
{
dsts_data_t dsts = {.d32 = 0 };
depctl_data_t depctl = {.d32 = 0 };
volatile uint32_t *addr;
int i, j;
uint32_t len;
if (dwc_ep->is_in)
dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
else
dwc_ep->desc_cnt =
dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
dwc_ep->bInterval;
/** Allocate descriptors for double buffering */
dwc_ep->iso_desc_addr =
dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
dwc_ep->desc_cnt * 2);
if (dwc_ep->desc_addr) {
DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
return;
}
dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
/** ISO OUT EP */
if (dwc_ep->is_in == 0) {
dev_dma_desc_sts_t sts = {.d32 = 0 };
dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
dma_addr_t dma_ad;
uint32_t data_per_desc;
dwc_otg_dev_out_ep_regs_t *out_regs =
core_if->dev_if->out_ep_regs[dwc_ep->num];
int offset;
addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
/** Buffer 0 descriptors setup */
dma_ad = dwc_ep->dma_addr0;
sts.b_iso_out.bs = BS_HOST_READY;
sts.b_iso_out.rxsts = 0;
sts.b_iso_out.l = 0;
sts.b_iso_out.sp = 0;
sts.b_iso_out.ioc = 0;
sts.b_iso_out.pid = 0;
sts.b_iso_out.framenum = 0;
offset = 0;
for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
i += dwc_ep->pkt_per_frm) {
for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
uint32_t len = (j + 1) * dwc_ep->maxpacket;
if (len > dwc_ep->data_per_frame)
data_per_desc =
dwc_ep->data_per_frame -
j * dwc_ep->maxpacket;
else
data_per_desc = dwc_ep->maxpacket;
len = data_per_desc % 4;
if (len)
data_per_desc += 4 - len;
sts.b_iso_out.rxbytes = data_per_desc;
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
offset += data_per_desc;
dma_desc++;
dma_ad += data_per_desc;
}
}
for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
uint32_t len = (j + 1) * dwc_ep->maxpacket;
if (len > dwc_ep->data_per_frame)
data_per_desc =
dwc_ep->data_per_frame -
j * dwc_ep->maxpacket;
else
data_per_desc = dwc_ep->maxpacket;
len = data_per_desc % 4;
if (len)
data_per_desc += 4 - len;
sts.b_iso_out.rxbytes = data_per_desc;
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
offset += data_per_desc;
dma_desc++;
dma_ad += data_per_desc;
}
sts.b_iso_out.ioc = 1;
len = (j + 1) * dwc_ep->maxpacket;
if (len > dwc_ep->data_per_frame)
data_per_desc =
dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
else
data_per_desc = dwc_ep->maxpacket;
len = data_per_desc % 4;
if (len)
data_per_desc += 4 - len;
sts.b_iso_out.rxbytes = data_per_desc;
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
dma_desc++;
/** Buffer 1 descriptors setup */
sts.b_iso_out.ioc = 0;
dma_ad = dwc_ep->dma_addr1;
offset = 0;
for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
i += dwc_ep->pkt_per_frm) {
for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
uint32_t len = (j + 1) * dwc_ep->maxpacket;
if (len > dwc_ep->data_per_frame)
data_per_desc =
dwc_ep->data_per_frame -
j * dwc_ep->maxpacket;
else
data_per_desc = dwc_ep->maxpacket;
len = data_per_desc % 4;
if (len)
data_per_desc += 4 - len;
data_per_desc =
sts.b_iso_out.rxbytes = data_per_desc;
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
offset += data_per_desc;
dma_desc++;
dma_ad += data_per_desc;
}
}
for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
data_per_desc =
((j + 1) * dwc_ep->maxpacket >
dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
j * dwc_ep->maxpacket : dwc_ep->maxpacket;
data_per_desc +=
(data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
sts.b_iso_out.rxbytes = data_per_desc;
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
offset += data_per_desc;
dma_desc++;
dma_ad += data_per_desc;
}
sts.b_iso_out.ioc = 1;
sts.b_iso_out.l = 1;
data_per_desc =
((j + 1) * dwc_ep->maxpacket >
dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
j * dwc_ep->maxpacket : dwc_ep->maxpacket;
data_per_desc +=
(data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
sts.b_iso_out.rxbytes = data_per_desc;
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
dwc_ep->next_frame = 0;
/** Write dma_ad into DOEPDMA register */
DWC_WRITE_REG32(&(out_regs->doepdma),
(uint32_t) dwc_ep->iso_dma_desc_addr);
}
/** ISO IN EP */
else {
dev_dma_desc_sts_t sts = {.d32 = 0 };
dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
dma_addr_t dma_ad;
dwc_otg_dev_in_ep_regs_t *in_regs =
core_if->dev_if->in_ep_regs[dwc_ep->num];
unsigned int frmnumber;
fifosize_data_t txfifosize, rxfifosize;
txfifosize.d32 =
DWC_READ_REG32(&core_if->dev_if->
in_ep_regs[dwc_ep->num]->dtxfsts);
rxfifosize.d32 =
DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
dma_ad = dwc_ep->dma_addr0;
dsts.d32 =
DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
sts.b_iso_in.bs = BS_HOST_READY;
sts.b_iso_in.txsts = 0;
sts.b_iso_in.sp =
(dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
sts.b_iso_in.ioc = 0;
sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
frmnumber = dwc_ep->next_frame;
sts.b_iso_in.framenum = frmnumber;
sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
sts.b_iso_in.l = 0;
/** Buffer 0 descriptors setup */
for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
dma_desc++;
dma_ad += dwc_ep->data_per_frame;
sts.b_iso_in.framenum += dwc_ep->bInterval;
}
sts.b_iso_in.ioc = 1;
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
++dma_desc;
/** Buffer 1 descriptors setup */
sts.b_iso_in.ioc = 0;
dma_ad = dwc_ep->dma_addr1;
for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
i += dwc_ep->pkt_per_frm) {
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
dma_desc++;
dma_ad += dwc_ep->data_per_frame;
sts.b_iso_in.framenum += dwc_ep->bInterval;
sts.b_iso_in.ioc = 0;
}
sts.b_iso_in.ioc = 1;
sts.b_iso_in.l = 1;
dma_desc->buf = dma_ad;
dma_desc->status.d32 = sts.d32;
dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
/** Write dma_ad into diepdma register */
DWC_WRITE_REG32(&(in_regs->diepdma),
(uint32_t) dwc_ep->iso_dma_desc_addr);
}
/** Enable endpoint, clear nak */
depctl.d32 = 0;
depctl.b.epena = 1;
depctl.b.usbactep = 1;
depctl.b.cnak = 1;
DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
depctl.d32 = DWC_READ_REG32(addr);
}
/**
* This function initializes a descriptor chain for Isochronous transfer
*
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP to start the transfer on.
*
*/
void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
dwc_ep_t * ep)
{
depctl_data_t depctl = {.d32 = 0 };
volatile uint32_t *addr;
if (ep->is_in) {
addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
} else {
addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
}
if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
return;
} else {
deptsiz_data_t deptsiz = {.d32 = 0 };
ep->xfer_len =
ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
ep->pkt_cnt =
(ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
ep->xfer_count = 0;
ep->xfer_buff =
(ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
ep->dma_addr =
(ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
if (ep->is_in) {
/* Program the transfer size and packet count
* as follows: xfersize = N * maxpacket +
* short_packet pktcnt = N + (short_packet
* exist ? 1 : 0)
*/
deptsiz.b.mc = ep->pkt_per_frm;
deptsiz.b.xfersize = ep->xfer_len;
deptsiz.b.pktcnt =
(ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
DWC_WRITE_REG32(&core_if->dev_if->
in_ep_regs[ep->num]->dieptsiz,
deptsiz.d32);
/* Write the DMA register */
DWC_WRITE_REG32(&
(core_if->dev_if->
in_ep_regs[ep->num]->diepdma),
(uint32_t) ep->dma_addr);
} else {
deptsiz.b.pktcnt =
(ep->xfer_len + (ep->maxpacket - 1)) /
ep->maxpacket;
deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
DWC_WRITE_REG32(&core_if->dev_if->
out_ep_regs[ep->num]->doeptsiz,
deptsiz.d32);
/* Write the DMA register */
DWC_WRITE_REG32(&
(core_if->dev_if->
out_ep_regs[ep->num]->doepdma),
(uint32_t) ep->dma_addr);
}
/** Enable endpoint, clear nak */
depctl.d32 = 0;
depctl.b.epena = 1;
depctl.b.cnak = 1;
DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
}
}
/**
* This function does the setup for a data transfer for an EP and
* starts the transfer. For an IN transfer, the packets will be
* loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
* the packets are unloaded from the Rx FIFO in the ISR.
*
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP to start the transfer on.
*/
static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
dwc_ep_t * ep)
{
if (core_if->dma_enable) {
if (core_if->dma_desc_enable) {
if (ep->is_in) {
ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
} else {
ep->desc_cnt = ep->pkt_cnt;
}
dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
} else {
if (core_if->pti_enh_enable) {
dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
} else {
ep->cur_pkt_addr =
(ep->proc_buf_num) ? ep->
xfer_buff1 : ep->xfer_buff0;
ep->cur_pkt_dma_addr =
(ep->proc_buf_num) ? ep->
dma_addr1 : ep->dma_addr0;
dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
}
}
} else {
ep->cur_pkt_addr =
(ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
ep->cur_pkt_dma_addr =
(ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
}
}
/**
* This function stops transfer for an EP and
* resets the ep's variables.
*
* @param core_if Programming view of DWC_otg controller.
* @param ep The EP to start the transfer on.
*/
void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
{
depctl_data_t depctl = {.d32 = 0 };
volatile uint32_t *addr;
if (ep->is_in == 1) {
addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
} else {
addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
}
/* disable the ep */
depctl.d32 = DWC_READ_REG32(addr);
depctl.b.epdis = 1;
depctl.b.snak = 1;
DWC_WRITE_REG32(addr, depctl.d32);
if (core_if->dma_desc_enable &&
ep->iso_desc_addr && ep->iso_dma_desc_addr) {
dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
ep->iso_dma_desc_addr,
ep->desc_cnt * 2);
}
/* reset varibales */
ep->dma_addr0 = 0;
ep->dma_addr1 = 0;
ep->xfer_buff0 = 0;
ep->xfer_buff1 = 0;
ep->data_per_frame = 0;
ep->data_pattern_frame = 0;
ep->sync_frame = 0;
ep->buf_proc_intrvl = 0;
ep->bInterval = 0;
ep->proc_buf_num = 0;
ep->pkt_per_frm = 0;
ep->pkt_per_frm = 0;
ep->desc_cnt = 0;
ep->iso_desc_addr = 0;
ep->iso_dma_desc_addr = 0;
}
int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
dwc_dma_t dma1, int sync_frame, int dp_frame,
int data_per_frame, int start_frame,
int buf_proc_intrvl, void *req_handle,
int atomic_alloc)
{
dwc_otg_pcd_ep_t *ep;
dwc_irqflags_t flags = 0;
dwc_ep_t *dwc_ep;
int32_t frm_data;
dsts_data_t dsts;
dwc_otg_core_if_t *core_if;
ep = get_ep_from_handle(pcd, ep_handle);
if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
DWC_WARN("bad ep\n");
return -DWC_E_INVALID;
}
DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
core_if = GET_CORE_IF(pcd);
dwc_ep = &ep->dwc_ep;
if (ep->iso_req_handle) {
DWC_WARN("ISO request in progress\n");
}
dwc_ep->dma_addr0 = dma0;
dwc_ep->dma_addr1 = dma1;
dwc_ep->xfer_buff0 = buf0;
dwc_ep->xfer_buff1 = buf1;
dwc_ep->data_per_frame = data_per_frame;
/** @todo - pattern data support is to be implemented in the future */
dwc_ep->data_pattern_frame = dp_frame;
dwc_ep->sync_frame = sync_frame;
dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
dwc_ep->proc_buf_num = 0;
dwc_ep->pkt_per_frm = 0;
frm_data = ep->dwc_ep.data_per_frame;
while (frm_data > 0) {
dwc_ep->pkt_per_frm++;
frm_data -= ep->dwc_ep.maxpacket;
}
dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
if (start_frame == -1) {
dwc_ep->next_frame = dsts.b.soffn + 1;
if (dwc_ep->bInterval != 1) {
dwc_ep->next_frame =
dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
dwc_ep->next_frame %
dwc_ep->bInterval);
}
} else {
dwc_ep->next_frame = start_frame;
}
if (!core_if->pti_enh_enable) {
dwc_ep->pkt_cnt =
dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
dwc_ep->bInterval;
} else {
dwc_ep->pkt_cnt =
(dwc_ep->data_per_frame *
(dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
- 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
}
if (core_if->dma_desc_enable) {
dwc_ep->desc_cnt =
dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
dwc_ep->bInterval;
}
if (atomic_alloc) {
dwc_ep->pkt_info =
DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
} else {
dwc_ep->pkt_info =
DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
}
if (!dwc_ep->pkt_info) {
DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
return -DWC_E_NO_MEMORY;
}
if (core_if->pti_enh_enable) {
dwc_memset(dwc_ep->pkt_info, 0,
sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
}
dwc_ep->cur_pkt = 0;
ep->iso_req_handle = req_handle;
DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
return 0;
}
int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle)
{
dwc_irqflags_t flags = 0;
dwc_otg_pcd_ep_t *ep;
dwc_ep_t *dwc_ep;
ep = get_ep_from_handle(pcd, ep_handle);
if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
DWC_WARN("bad ep\n");
return -DWC_E_INVALID;
}
dwc_ep = &ep->dwc_ep;
dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
DWC_FREE(dwc_ep->pkt_info);
DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
if (ep->iso_req_handle != req_handle) {
DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
return -DWC_E_INVALID;
}
DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
ep->iso_req_handle = 0;
return 0;
}
/**
* This function is used for perodical data exchnage between PCD and gadget drivers.
* for Isochronous EPs
*
* - Every time a sync period completes this function is called to
* perform data exchange between PCD and gadget
*/
void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
void *req_handle)
{
int i;
dwc_ep_t *dwc_ep;
dwc_ep = &ep->dwc_ep;
DWC_SPINUNLOCK(ep->pcd->lock);
pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
dwc_ep->proc_buf_num ^ 0x1);
DWC_SPINLOCK(ep->pcd->lock);
for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
dwc_ep->pkt_info[i].status = 0;
dwc_ep->pkt_info[i].offset = 0;
dwc_ep->pkt_info[i].length = 0;
}
}
int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
void *iso_req_handle)
{
dwc_otg_pcd_ep_t *ep;
dwc_ep_t *dwc_ep;
ep = get_ep_from_handle(pcd, ep_handle);
if (!ep->desc || ep->dwc_ep.num == 0) {
DWC_WARN("bad ep\n");
return -DWC_E_INVALID;
}
dwc_ep = &ep->dwc_ep;
return dwc_ep->pkt_cnt;
}
void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
void *iso_req_handle, int packet,
int *status, int *actual, int *offset)
{
dwc_otg_pcd_ep_t *ep;
dwc_ep_t *dwc_ep;
ep = get_ep_from_handle(pcd, ep_handle);
if (!ep)
DWC_WARN("bad ep\n");
dwc_ep = &ep->dwc_ep;
*status = dwc_ep->pkt_info[packet].status;
*actual = dwc_ep->pkt_info[packet].length;
*offset = dwc_ep->pkt_info[packet].offset;
}
#endif /* DWC_EN_ISOC */