Allow to pass all module timings in the format (ck, ns) #231
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Merged
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Thanks @jedrzejboczar for splitting #224 in smaller PRs, this looks good (the others PRs too). I'll have a closer look and test/merge in the next days. |
enjoy-digital
approved these changes
Feb 2, 2021
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Thanks @jedrzejboczar, this looks good. I also did some comparisons of the generated verilog before and after applying this PR on various targets and the timings are computed identically.
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This is a part of splitting #224 into smaller PRs.
This PR makes it possible to pass all timings as
(ck, ns)tuples (herenscan beNone) or justnsfloat.