core/LiteJESD204BCoreRX/register_jsync: Fix default polarity.

litejesd204b/core.py

@@ -309,7 +309,7 @@ def __init__(self, phys, jesd_settings, converter_data_width, scrambling=True, i
             ),
         ]
 
-    def register_jsync(self, jsync, polarity=0b1):
+    def register_jsync(self, jsync, polarity=0b0):
         self.jsync_registered = True
         _jsync = Signal()
         self.comb += _jsync.eq({0b0: self.jsync, 0b1:~self.jsync}[polarity])