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Hi everyone
While everything is working fine with vexriscv architecture, we are able to boot bare-metal, linux and RTOS without any issue (with some few changes in dts and core py files and DDR3 issues) same we are not getting any out after liftoff on RocketChip architecture.
Is there any open issue with booting with Rocket Chip ?
Generation of bit stream.
litex-boards/litex_boards/targets/xilinx_ac701.py --build --cpu-type rocket --cpu-variant linux4 --sys-clk-freq 50e6 --with-ethernet
--> Bitstream generated successfully
--> BIOS running on Hardware successfully. All test cases passed including SDRAM.
Generation of demo.bin (baremetal)
litex_bare_metal_demo --build-path=./
Loading demo.bin via lxterm via serial port to AC701 hardware
sudo lxterm /dev/ttyUSB1 --kernel demo.bin --kernel-adr 0x80000000
While this does work it also breaks some other stuff.
The real issue is that the version of the toolchain that you and I were using is broken.
Update your toolchain to a more recent on like this and it should work again.
Hi everyone
While everything is working fine with vexriscv architecture, we are able to boot bare-metal, linux and RTOS without any issue (with some few changes in dts and core py files and DDR3 issues) same we are not getting any out after liftoff on RocketChip architecture.
Is there any open issue with booting with Rocket Chip ?
Generation of bit stream.
litex-boards/litex_boards/targets/xilinx_ac701.py --build --cpu-type rocket --cpu-variant linux4 --sys-clk-freq 50e6 --with-ethernet
--> Bitstream generated successfully
--> BIOS running on Hardware successfully. All test cases passed including SDRAM.
Generation of demo.bin (baremetal)
litex_bare_metal_demo --build-path=./
Loading demo.bin via lxterm via serial port to AC701 hardware
sudo lxterm /dev/ttyUSB1 --kernel demo.bin --kernel-adr 0x80000000
After Liftoff, unable to get any output from demo.bin, We are stuck here :(
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