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             Copyright 2012-2022 / Enjoy-Digital & LiteX developers

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Welcome to LiteX!

The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create full FPGA based systems.

LiteX SoC builder framework quick tour/overview: Slides

Want to get started and/or looking for documentation? Make sure to visit the Wiki!

A question or want to get in touch? Our IRC channel is [#litex at irc.libera.chat].

LiteX provides all the common components required to easily create an FPGA Core/SoC:

  • ✔️ Buses and Streams (Wishbone, AXI, Avalon-ST) and their interconnect.
  • ✔️ Simple cores: RAM, ROM, Timer, UART, JTAG, etc….
  • ✔️ Complex cores through the ecosystem of cores: LiteDRAM, LitePCIe, LiteEth, LiteSATA, etc...
  • ✔️ Various CPUs & ISAs: RISC-V, OpenRISC, LM32, Zynq, X86 (through a PCIe), etc...
  • ✔️ Mixed languages support with VHDL/Verilog/(n)Migen/Spinal-HDL/etc... integration capabilities.
  • ✔️ Powerful debug infrastructure through the various bridges and Litescope.
  • ✔️ Direct/Fast simulation through Verilator.
  • ✔️ Build backends for open-source and vendors toolchains.
  • ✔️ And a lot more... :)

By combining LiteX with the ecosystem of cores, creating complex SoCs becomes a lot easier than with traditional approaches while providing better portability and flexibility: Here is for example a Multi-core Linux Capable SoC based on VexRiscv-SMP CPU, LiteDRAM, LiteSATA built and integrated with LiteX, running on a cheap repurposed Acorn CLE215+ Mining Board: For more info, have a look at Linux-on-LiteX-Vexriscv project and try running Linux on your FPGA board!

LiteX's digital logic is currently described with Migen which does not prevent users to create mixed language projects:

  • It's very common and easy to integrate VHDL/Verilog/SystemVerilog/nMigen/Spinal-HDL code in LiteX!
  • It's also very common to do the opposite and generate the LiteX design as a verilog file and integrate it in a traditional flow.

LiteX was initially developed by Enjoy-Digital to create projects for clients (and we are still using it for that :)) and trying to take the different clients' requirements/needs consideration made, we think, the framework very flexible:

  • Some users only want to use it to easily interconnect their existing VHDL/Verilog/SV cores.
  • Some users are only interested to reuse the PCIe/Ethernet/SATA/etc cores as regular core and just integrate them in their traditional flow.
  • Some users with a hardware background start with the above approaches and then switch later to the full Python flow since find it more efficient.
  • Some users with a software background and fluent with Python start playing with FPGAs while they would probably never touch FPGA otherwise :)
  • Etc...

We are well aware that everyone has a different background, so it's up to you to pick the right approach with LiteX that will be convenient for you!

To get started we encourage you to read the wiki.

You already have a FPGA board(s)? Visit LiteX-Boards to see if your board(s) is already supported!

The framework is also far from perfect and we'll be happy to have your feedback or/and contributions.

Have fun! 😉

Typical LiteX design flow:

                                      +---------------+
                                      |FPGA toolchains|
                                      +----^-----+----+
                                           |     |
                                        +--+-----v--+
                       +-------+        |           |
                       | Migen +-------->           |
                       +-------+        |           |        Your design
                                        |   LiteX   +---> ready to be used!
                                        |           |
              +----------------------+  |           |
              |LiteX Cores Ecosystem +-->           |
              +----------------------+  +-^-------^-+
               (Eth, SATA, DRAM, USB,     |       |
                PCIe, Video, etc...)      +       +
                                         board   target
                                         file    file

LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32, BlackParrot and is compatible with the LiteX's Cores Ecosystem:

Name Build Status Description
LiteX-Boards Boards support
LiteDRAM DRAM
LiteEth Ethernet
LitePCIe PCIe
LiteSATA SATA
LiteSDCard SD card
LiteICLink Inter-Chip communication
LiteJESD204B JESD204B
LiteSPI SPI/SPI-Flash
LiteScope Logic analyzer

Examples of designs built with LiteX:

Custom PCIe SDI Capture/Playback board built around LitePCIe and integrated with LiteX, allowing full control of the SDI flow and very low latency. Alternative firmware/gateware for the SDS1104X-E Scope: enter image description here HBM2 test infrastructure on Forest Kitten 33: enter image description here

To discover more products/projects built with LiteX, visit the projects page on the Wiki.

Papers, Presentations, Tutorials, Links

FPGA lessons/tutorials:

Migen tutorial:

OSDA 2019 paper/slides:

Linux on LiteX-Vexriscv:

RISC-V Getting Started Guide:

LiteX vs. Vivado First Impressions:

35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:

Tim has to many projects - LatchUp Edition: https://www.youtube.com/watch?v=v7WrTmexod0

Sub-packages

litex.gen Provides specific or experimental modules to generate HDL that are not integrated in Migen.

litex.build: Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.

litex.soc: Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.

Quick start guide

  1. Install Python 3.6+ and FPGA vendor's development tools and/or Verilator.
  2. Install Migen/LiteX and the LiteX's cores:
$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$ chmod +x litex_setup.py
$ ./litex_setup.py --init --install --user (--user to install to user directory) --config=(minimal, standard, full)

Later, if you need to update all repositories:

$ ./litex_setup.py --update

Note: On MacOS, make sure you have HomeBrew installed. Then do, brew install wget.

Note: On Windows, it's possible you'll have to set SHELL environment variable to SHELL=cmd.exe.

  1. Install a RISC-V toolchain (Only if you want to test/create a SoC with a CPU):
$ pip3 install meson ninja
$ ./litex_setup.py --gcc=riscv
  1. Build the target of your board...:

Go to litex-boards/litex_boards/targets and execute the target you want to build.

  1. ... and/or install Verilator and test LiteX directly on your computer without any FPGA board:

On Linux (Ubuntu):

$ sudo apt install libevent-dev libjson-c-dev verilator
$ litex_sim --cpu-type=vexriscv

On MacOS:

$ brew install json-c verilator libevent
$ brew cask install tuntap
$ litex_sim --cpu-type=vexriscv
  1. Run a terminal program on the board's serial port at 115200 8-N-1.

You should get the BIOS prompt like the one below.

Community

Over the years a friendly community has grown around LiteX and the ecosystem of cores. Feedbacks and contributions have already greatly improved the project, EnjoyDigital still leads the development but it is now a community project and collaborative projects created around/with LiteX can be found at https://github.com/litex-hub.

Contact

E-mail: florent@enjoy-digital.fr