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Add example for embedding a LiteX SOC into Vivado project for Zynq #1910
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If I correctly understood your attempt you wish to use the ARM processor ( If so: why not using
This is working on most of the Zynq based board supported by LiteX (see If your target board hasn't been already tested/validated in this use case (as |
I have check some zynq boards. Some zynq board use a xci file for hard zynq core (like redpitaya) , some use preset (not every board has preset) or tcl config (only see arty_z7). I am not fimilar with these methods, and not confident to generate a working PS core. I try use a self make xci, for some reason not working. In the example I show, I can change PS ip using "Customize Block GUI" any time after genrate liteX soc. I can then develop apps using Vitis or petalinux (in theory, haven't tried), which provide easy enviremnet for build and debugging. I understand that liteX in flavor, software build can be intergrated in Python work flow. But for beginners like me, an IDE with some template projects will get me start very quickly. |
Hi @benfre, thanks for the feedback and detailed explanations. This indeed is a nice way to integrate things and could be convenients for users familiar with Vivado Block Design. We are also using a similar approach to package/integrate different cores (ex LiteDRAM, LitePCIe, LiteEth, etc...) for users also using Vivado Block Design. I'll have a closer look a it and if you are OK with it, this could probably be a nice tutorial to be included in the wiki! |
I'm OK with this.
Please have a closer look. I'm not familiar with migen or LiteX. This example take me couples of weeks to get working. The only AXI-lite interface and address width issue can have some fixes. |
There is a few attempts to works with Xilinx SOCs with Hard ARM cores. I find these examples difficult to follow.
The example below is what i tried, and finally worked.
The principle is this: add AXI interfaces (slave or master) to LiteX soc, generate a verilog file, and put in Vivado project. That's it.
In theory you can add as many AXI interfaces as you can, remapped to different address regions, use in ARM core standalone app or as Petalinux devices.
Create SOC with AXI-lite interface
_io
sys
clock and reset.The AXI-lite interface only works with 32bit address width, limited in remapper to a small region.
Build SOC with liteX
Build soc with compiling BIOS, generating ROM files needed in SOC verilog file
Add generated verilog file to Vivado project
Add the SOC verilog source file, drag to a block design. Example with ZYNQ7020, add as a slave under GP0, together with AXI-GPIO and AXI-IIC ip.
Assign embed SOC address space, (
0x6000_0000
in example, and size ? matched in soc)Make soc pads external (with same names) and copy part of
xdc
file generated by liteXGenerate bitstream file
Vitis app Test
An standalone app in ARM core0, call
leds_out_write(7);
to stop the LED Chaser.Manually disable uart functions in
csr.h
, as it is conflicted with ZYNQ PS libraryManually change CSR_BASE to
0x60000000L
as its assigned in VivadoDebug the app, LED stop chasing after
led_out_write
callBIOS serial port also works
In VexRiscv, CSR is mapped in
0xF000_0000
, not0x6000_0000
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