VexRiscv Minimal variant won't boot

[jedrzejboczar]

Initially, the problem was wrong cdelay in simulation wiht the "minimal" variant of VexRiscv as described here: enjoy-digital/litedram#255 (comment).

I wanted to measure the delays on real hardware, so I applied the following patch: measure-cdelay.zip and built for the Arty target. The execution stops after printing Measure:. When using variant "lite" everything works fine and the elapsed time is printed.

Then I reverted the patch and just built with all defaults using:

python litex-boards/litex_boards/targets/digilent_arty.py --cpu-variant minimal --load --build

and the execution stops after the line BIOS built on Jun 10 2021 11:04:03, so on the crcbios(); and there is no more output.

[enjoy-digital]

@jedrzejboczar: I just tested it and it works correctly. The possible issue was probably that the BIOS required a full rebuild do to the fact that Minimal variant only supports rv32i. With 44b223a, the BIOS will now automatically be fully rebuilt in this case.