pci: Nailed down ROM_PMEM_OFFSET

envytools · Sep 16, 2016 · 73e1921 · 73e1921
1 parent a6a1dc5
commit 73e1921
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/rnndb/bus/pci.xml b/rnndb/bus/pci.xml
@@ -421,6 +421,9 @@
 	</reg32>
 	<reg32 offset="0x1c8" name="P2P_READ_REPLY_ADDR_LOW" stride="8" length="3" variants="G80:GF100"/>
 	<reg32 offset="0x1cc" name="P2P_READ_REPLY_ADDR_HIGH" stride="8" length="3" variants="G80:GF100"/>
+	<!-- if ROM_SHADOW_ENABLE is on, accesses to PCI ROM space go to PMEM
+	     window at offset (PCI ROM access offset | ROM_PMEM_OFFSET). -->
+	<reg32 offset="0x418" name="ROM_PMEM_OFFSET" variants="G80:" align="0x1000" max="0xff000"/>
 	<!-- XXX: 420+ is AER -->
 	<reg32 offset="0x460" name="CONFIG_LINK" variants="G84:GK104">
 		<bitfield pos="0" name="COMMIT"/>