(Original readme for the template repository here)

This repo is an experiment in using Verilog source files instead of Wokwi diagrams for TinyTapeout, it solves the classic problem of diving a clock by 3, with a 50% duty cycle, using no sequential cells. It's more or less an answer to execise 26.7 in Digital Design by Dally.

The verilog code is in src/user_module_340067262721426004.v