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When a module is declared without parameters, the file is incorrectly formatted and the comments for the parameters are removed.
Original source to format
`timescale 1ns / 1ps
module stimulus;
// Inputs
reg[1:0] x;
reg[1:0] y;
// Outputs
wire z;
// Instantiate the Unit Under Test (UUT)
comparator2bit uut (
.x(x),
.y(y),
.z(z)
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0,stimulus);
// Initialize Inputs
x = 0;
y = 0;
#20 x = 1;
#20 y = 1;
#20 y = 3;
#20 x = 3;
#20 y = 1;
#20 y = 0;
#40 ;
end
initial begin
$monitor("t = %3d x = %2b,y = %2b,z = %d \n",$time,x,y,z,);
end
endmodule
Format result without braces:
`timescale 1ns / 1ps
module stimulus; reg[1:0] x; reg[1:0] y; wire z; comparator2bit uut (.x(x), .y(y), .z(z));
initial begin
$dumpfile("test.vcd");
$dumpvars(0,stimulus);
// Initialize Inputs
x = 0;
y = 0;
#20 x = 1;
#20 y = 1;
#20 y = 3;
#20 x = 3;
#20 y = 1;
#20 y = 0;
#40 ;
end
initial begin
$monitor("t = %3d x = %2b,y = %2b,z = %d \n",$time,x,y,z,);
end
endmodule
Please note that the comments at the beginning were totaly removed!
Format result adding braces to stimulus:
`timescale 1ns / 1ps
module stimulus();
// Inputs
reg[1:0] x;
reg[1:0] y;
// Outputs
wire z;
// Instantiate the Unit Under Test (UUT)
comparator2bit uut (
.x(x),
.y(y),
.z(z)
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0,stimulus);
// Initialize Inputs
x = 0;
y = 0;
#20 x = 1;
#20 y = 1;
#20 y = 3;
#20 x = 3;
#20 y = 1;
#20 y = 0;
#40 ;
end
initial begin
$monitor("t = %3d x = %2b,y = %2b,z = %d \n",$time,x,y,z,);
end
endmodule
The text was updated successfully, but these errors were encountered:
When a
module
is declared without parameters, the file is incorrectly formatted and the comments for the parameters are removed.Original source to format
Format result without braces:
Please note that the comments at the beginning were totaly removed!
Format result adding braces to
stimulus
:The text was updated successfully, but these errors were encountered: