var. name who start with "if" will cause mistake

[andythebreaker]

for example i have a code:

if (ifmap[6] == 1) begin
                            p = p + ({{24{1'b1}}, (ifmap[7]?((~((~(ifmap-1)) << 1))+1):(ifmap<<1))})<<i;
                            end else begin
                                p = p + ({24'b0, (ifmap[7]?((~((~(ifmap-1)) << 1))+1):(ifmap<<1))})<<i;
                            end
                            $display("\\011 = >2/");
                        end

where ifmap is a input, but [ericsonj ](https://github.com/ericsonj)/ [verilog-format](https://github.com/ericsonj/verilog-format) will see it as if and map, which is not correct!
the out come is like:

if (if map[6] == 1) begin
                            p = p + ({{24{1'b1}}, (ifmap[7]?((~((~(ifmap-1)) << 1))+1):(ifmap<<1))})<<i;
                            end else begin
                                p = p + ({24'b0, (ifmap[7]?((~((~(ifmap-1)) << 1))+1):(ifmap<<1))})<<i;
                            end
                            $display("\\011 = >2/");
                        end

the correct version need to be like if (ifmap[6] == 1) begin