Update lib.rs

erihsu · Apr 29, 2021 · f2c57e1 · f2c57e1
1 parent 13139b4
commit f2c57e1
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/src/lib.rs b/src/lib.rs
@@ -11,9 +11,9 @@ pub trait CTSPlugin {
     // given clock network name, return a set of sinks. The information include sink name, sink location
     fn get_clock_sinks(&self, clk:&str) -> CTSPluginRes<Vec<(String, (i32, i32))>>;
     // given clock net name, clock net Route Definition, change the internal design
-    fn update_clock_net(&mut self,net_name:&str, net: &[Path]) -> CTSPluginRes<()>;
-    // given buffer model, buffer location and orientation, change the internal design, return new clock net name
-    fn insert_clock_buffer(&mut self,buffer_name:&str, model:&str, location:(i32, i32)) -> CTSPluginRes<String>;
+    fn update_clock_net(&mut self,net_name:&str, net_data: &[Path]) -> CTSPluginRes<()>;
+    // given buffer model, buffer location, net name being hold up, change the internal design, return new clock net name
+    fn insert_clock_buffer(&mut self,buffer_name:&str, model:&str, location:(i32, i32),net_name:&str) -> CTSPluginRes<String>;
     // export standard def file
     fn export_def(&self, path: &str) -> CTSPluginRes<()>;
     // export verilog netlist