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* maint:
  Update configure scripts
  make: Fix configure test for ISB/cache control on ARM
  erts: Fix out-of-bounds copy in load_nif_1st_finisher
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@jhogberg
jhogberg committed Feb 7, 2023
2 parents 1fb4755 + 9069214 commit 1c1cc59
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Showing 6 changed files with 186 additions and 20 deletions.
20 changes: 10 additions & 10 deletions erts/config.h.in
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Original file line number Diff line number Diff line change
Expand Up @@ -138,6 +138,11 @@
/* Define if you have all ethread defines */
#undef ETHR_HAVE_ETHREAD_DEFINES

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'dc cvau' instruction, and are compiling for
an ARM processor with ARM DC instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'dmb sy' instruction, and are compiling for
an ARM processor with ARM DMB instruction support, or not */
Expand All @@ -153,21 +158,16 @@
an ARM processor with ARM DMB instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'isb sy' instruction, and are compiling for
an ARM processor with ARM ISB instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_ISB_SY_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'dc cvau' instruction, and are compiling for
an ARM processor with ARM DC instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'ic ivau' instruction, and are compiling for
an ARM processor with ARM IC instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'isb sy' instruction, and are compiling for
an ARM processor with ARM ISB instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_ISB_SY_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc __atomic builtins or
not */
#undef ETHR_HAVE_GCC___ATOMIC_BUILTINS
Expand Down
16 changes: 7 additions & 9 deletions erts/configure
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Original file line number Diff line number Diff line change
Expand Up @@ -14072,6 +14072,8 @@ printf "%s\n" "#define ETHR_HAVE___atomic_compare_exchange_n $have_atomic_ops" >
ethr_arm_dbm_st_instr_val=0
ethr_arm_dbm_ld_instr_val=0
ethr_arm_isb_sy_instr_val=0
ethr_arm_dc_cvau_instr_val=0
ethr_arm_ic_ivau_instr_val=0
case "$GCC-$host_cpu" in #(
yes-arm*|yes-aarch*) :

Expand Down Expand Up @@ -14213,7 +14215,6 @@ printf "%s\n" "$ethr_cv_arm_isb_sy_instr" >&6; }
if test $ethr_cv_arm_isb_sy_instr = yes; then
ethr_arm_isb_sy_instr_val=1
fi

{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'dc cvau' instruction" >&5
printf %s "checking for ARM 'dc cvau' instruction... " >&6; }
if test ${ethr_cv_arm_dc_cvau_instr+y}
Expand All @@ -14228,8 +14229,8 @@ else $as_nop
int
main (void)
{
char data[512];
__asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");

char data[512]; __asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");

;
return 0;
Expand All @@ -14248,7 +14249,6 @@ printf "%s\n" "$ethr_cv_arm_dc_cvau_instr" >&6; }
if test $ethr_cv_arm_dc_cvau_instr = yes; then
ethr_arm_dc_cvau_instr_val=1
fi

{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'ic ivau' instruction" >&5
printf %s "checking for ARM 'ic ivau' instruction... " >&6; }
if test ${ethr_cv_arm_ic_ivau_instr+y}
Expand All @@ -14263,8 +14263,8 @@ else $as_nop
int
main (void)
{
char data[512];
__asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");

char data[512]; __asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");

;
return 0;
Expand All @@ -14281,9 +14281,8 @@ fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_ic_ivau_instr" >&5
printf "%s\n" "$ethr_cv_arm_ic_ivau_instr" >&6; }
if test $ethr_cv_arm_ic_ivau_instr = yes; then
ethr_arm_dc_cvau_instr_val=1
ethr_arm_ic_ivau_instr_val=1
fi

;; #(
*) :
;;
Expand All @@ -14308,7 +14307,6 @@ printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION $ethr_arm_dc_cv
printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION $ethr_arm_ic_ivau_instr_val" >>confdefs.h



test $ethr_cv_32bit___sync_val_compare_and_swap = yes &&
ethr_have_gcc_native_atomics=yes
test $ethr_cv_64bit___sync_val_compare_and_swap = yes &&
Expand Down
3 changes: 2 additions & 1 deletion erts/emulator/beam/erl_nif.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5024,7 +5024,8 @@ static void load_nif_1st_finisher(void* vlib)
char *code_rw = (char*)erts_codeinfo_to_code(ci_rw);
const char *src = fin->beam_stubv[i].code.call_nif;

size_t cpy_sz = sizeof(fin->beam_stubv[0].code.call_nif);
size_t cpy_sz = sizeof(fin->beam_stubv[0].code.call_nif) -
BEAM_ASM_FUNC_PROLOGUE_SIZE;

sys_memcpy(&code_rw[BEAM_ASM_FUNC_PROLOGUE_SIZE],
&src[BEAM_ASM_FUNC_PROLOGUE_SIZE],
Expand Down
15 changes: 15 additions & 0 deletions lib/erl_interface/config.h.in
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,11 @@
/* Define if 'errno' should not be exposed as is in 'erl_errno' */
#undef EI_HIDE_REAL_ERRNO

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'dc cvau' instruction, and are compiling for
an ARM processor with ARM DC instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'dmb sy' instruction, and are compiling for
an ARM processor with ARM DMB instruction support, or not */
Expand All @@ -21,6 +26,16 @@
an ARM processor with ARM DMB instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'ic ivau' instruction, and are compiling for
an ARM processor with ARM IC instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc compatible compiler
capable of generating the ARM 'isb sy' instruction, and are compiling for
an ARM processor with ARM ISB instruction support, or not */
#undef ETHR_HAVE_GCC_ASM_ARM_ISB_SY_INSTRUCTION

/* Define as a boolean indicating whether you have a gcc __atomic builtins or
not */
#undef ETHR_HAVE_GCC___ATOMIC_BUILTINS
Expand Down
115 changes: 115 additions & 0 deletions lib/erl_interface/configure
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8593,6 +8593,9 @@ printf "%s\n" "#define ETHR_HAVE___atomic_compare_exchange_n $have_atomic_ops" >
ethr_arm_dbm_sy_instr_val=0
ethr_arm_dbm_st_instr_val=0
ethr_arm_dbm_ld_instr_val=0
ethr_arm_isb_sy_instr_val=0
ethr_arm_dc_cvau_instr_val=0
ethr_arm_ic_ivau_instr_val=0
case "$GCC-$host_cpu" in #(
yes-arm*|yes-aarch*) :

Expand Down Expand Up @@ -8700,6 +8703,108 @@ printf "%s\n" "$ethr_cv_arm_dbm_ld_instr" >&6; }
if test $ethr_cv_arm_dbm_ld_instr = yes; then
ethr_arm_dbm_ld_instr_val=1
fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'isb sy' instruction" >&5
printf %s "checking for ARM 'isb sy' instruction... " >&6; }
if test ${ethr_cv_arm_isb_sy_instr+y}
then :
printf %s "(cached) " >&6
else $as_nop

ethr_cv_arm_isb_sy_instr=no
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
/* end confdefs.h. */
int
main (void)
{
__asm__ __volatile__("isb sy" : : : "memory");
;
return 0;
}
_ACEOF
if ac_fn_c_try_link "$LINENO"
then :
ethr_cv_arm_isb_sy_instr=yes
fi
rm -f core conftest.err conftest.$ac_objext conftest.beam \
conftest$ac_exeext conftest.$ac_ext

fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_isb_sy_instr" >&5
printf "%s\n" "$ethr_cv_arm_isb_sy_instr" >&6; }
if test $ethr_cv_arm_isb_sy_instr = yes; then
ethr_arm_isb_sy_instr_val=1
fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'dc cvau' instruction" >&5
printf %s "checking for ARM 'dc cvau' instruction... " >&6; }
if test ${ethr_cv_arm_dc_cvau_instr+y}
then :
printf %s "(cached) " >&6
else $as_nop

ethr_cv_arm_dc_cvau_instr=no
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
/* end confdefs.h. */
int
main (void)
{
char data[512]; __asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");
;
return 0;
}
_ACEOF
if ac_fn_c_try_link "$LINENO"
then :
ethr_cv_arm_dc_cvau_instr=yes
fi
rm -f core conftest.err conftest.$ac_objext conftest.beam \
conftest$ac_exeext conftest.$ac_ext

fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_dc_cvau_instr" >&5
printf "%s\n" "$ethr_cv_arm_dc_cvau_instr" >&6; }
if test $ethr_cv_arm_dc_cvau_instr = yes; then
ethr_arm_dc_cvau_instr_val=1
fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'ic ivau' instruction" >&5
printf %s "checking for ARM 'ic ivau' instruction... " >&6; }
if test ${ethr_cv_arm_ic_ivau_instr+y}
then :
printf %s "(cached) " >&6
else $as_nop

ethr_cv_arm_ic_ivau_instr=no
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
/* end confdefs.h. */
int
main (void)
{
char data[512]; __asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");
;
return 0;
}
_ACEOF
if ac_fn_c_try_link "$LINENO"
then :
ethr_cv_arm_ic_ivau_instr=yes
fi
rm -f core conftest.err conftest.$ac_objext conftest.beam \
conftest$ac_exeext conftest.$ac_ext

fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_ic_ivau_instr" >&5
printf "%s\n" "$ethr_cv_arm_ic_ivau_instr" >&6; }
if test $ethr_cv_arm_ic_ivau_instr = yes; then
ethr_arm_ic_ivau_instr_val=1
fi
;; #(
*) :
;;
Expand All @@ -8714,6 +8819,16 @@ printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION $ethr_arm_dbm_st

printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION $ethr_arm_dbm_ld_instr_val" >>confdefs.h


printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_ISB_SY_INSTRUCTION $ethr_arm_isb_sy_instr_val" >>confdefs.h


printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION $ethr_arm_dc_cvau_instr_val" >>confdefs.h


printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION $ethr_arm_ic_ivau_instr_val" >>confdefs.h


test $ethr_cv_32bit___sync_val_compare_and_swap = yes &&
ethr_have_gcc_native_atomics=yes
test $ethr_cv_64bit___sync_val_compare_and_swap = yes &&
Expand Down
37 changes: 37 additions & 0 deletions make/autoconf/otp.m4
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1415,6 +1415,9 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
ethr_arm_dbm_sy_instr_val=0
ethr_arm_dbm_st_instr_val=0
ethr_arm_dbm_ld_instr_val=0
ethr_arm_isb_sy_instr_val=0
ethr_arm_dc_cvau_instr_val=0
ethr_arm_ic_ivau_instr_val=0
AS_CASE(
["$GCC-$host_cpu"],
[yes-arm*|yes-aarch*],
Expand Down Expand Up @@ -1451,11 +1454,45 @@ AC_DEFUN(ETHR_CHK_GCC_ATOMIC_OPS,
if test $ethr_cv_arm_dbm_ld_instr = yes; then
ethr_arm_dbm_ld_instr_val=1
fi
AC_CACHE_CHECK([for ARM 'isb sy' instruction], ethr_cv_arm_isb_sy_instr,
[
ethr_cv_arm_isb_sy_instr=no
AC_LINK_IFELSE([AC_LANG_PROGRAM([[]], [[
__asm__ __volatile__("isb sy" : : : "memory");
]])],[ethr_cv_arm_isb_sy_instr=yes],[])
])
if test $ethr_cv_arm_isb_sy_instr = yes; then
ethr_arm_isb_sy_instr_val=1
fi
AC_CACHE_CHECK([for ARM 'dc cvau' instruction], ethr_cv_arm_dc_cvau_instr,
[
ethr_cv_arm_dc_cvau_instr=no
AC_LINK_IFELSE([AC_LANG_PROGRAM([[]], [[
char data[512]; __asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");
]])],[ethr_cv_arm_dc_cvau_instr=yes],[])
])
if test $ethr_cv_arm_dc_cvau_instr = yes; then
ethr_arm_dc_cvau_instr_val=1
fi
AC_CACHE_CHECK([for ARM 'ic ivau' instruction], ethr_cv_arm_ic_ivau_instr,
[
ethr_cv_arm_ic_ivau_instr=no
AC_LINK_IFELSE([AC_LANG_PROGRAM([[]], [[
char data[512]; __asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");
]])],[ethr_cv_arm_ic_ivau_instr=yes],[])
])
if test $ethr_cv_arm_ic_ivau_instr = yes; then
ethr_arm_ic_ivau_instr_val=1
fi
])
AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_DMB_INSTRUCTION], [$ethr_arm_dbm_sy_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'dmb sy' instruction, and are compiling for an ARM processor with ARM DMB instruction support, or not])
AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION], [$ethr_arm_dbm_st_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'dmb st' instruction, and are compiling for an ARM processor with ARM DMB instruction support, or not])
AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION], [$ethr_arm_dbm_ld_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'dmb ld' instruction, and are compiling for an ARM processor with ARM DMB instruction support, or not])
AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_ISB_SY_INSTRUCTION], [$ethr_arm_isb_sy_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'isb sy' instruction, and are compiling for an ARM processor with ARM ISB instruction support, or not])
AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION], [$ethr_arm_dc_cvau_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'dc cvau' instruction, and are compiling for an ARM processor with ARM DC instruction support, or not])
AC_DEFINE_UNQUOTED([ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION], [$ethr_arm_ic_ivau_instr_val], [Define as a boolean indicating whether you have a gcc compatible compiler capable of generating the ARM 'ic ivau' instruction, and are compiling for an ARM processor with ARM IC instruction support, or not])
test $ethr_cv_32bit___sync_val_compare_and_swap = yes &&
ethr_have_gcc_native_atomics=yes
test $ethr_cv_64bit___sync_val_compare_and_swap = yes &&
Expand Down

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