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JIT: Fix incorrect code generation for div/rem sequence #5409

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merged 1 commit into from Nov 19, 2021
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9 changes: 8 additions & 1 deletion erts/emulator/beam/predicates.tab
Expand Up @@ -217,5 +217,12 @@ pred.map_key_sort(Size, Rest) {

// Test that the two registers are distinct.
pred.distinct(Reg1, Reg2) {
return Reg1.type != Reg2.type || Reg1.val != Reg2.val;
if (Reg1.type != Reg2.type) {
return 1;
} else if (Reg1.type == TAG_x || Reg1.type == TAG_y) {
/* We must not compare the type indices (if any). */
return (Reg1.val & REG_MASK) != (Reg2.val & REG_MASK);
} else {
return Reg1.val != Reg2.val;
}
}
30 changes: 28 additions & 2 deletions erts/emulator/test/op_SUITE.erl
Expand Up @@ -23,7 +23,8 @@
-include_lib("common_test/include/ct.hrl").

-export([all/0, suite/0,
bsl_bsr/1,logical/1,t_not/1,relop_simple/1,relop/1,complex_relop/1]).
bsl_bsr/1,logical/1,t_not/1,relop_simple/1,relop/1,
complex_relop/1,unsafe_fusing/1]).

-export([]).
-import(lists, [foldl/3,flatmap/2]).
Expand All @@ -34,7 +35,7 @@ suite() ->

all() ->
[bsl_bsr, logical, t_not, relop_simple, relop,
complex_relop].
complex_relop, unsafe_fusing].

%% Test the bsl and bsr operators.
bsl_bsr(Config) when is_list(Config) ->
Expand Down Expand Up @@ -424,6 +425,31 @@ eval(E0) ->
{value,Val,_Bs} -> Val
end.

unsafe_fusing(_Config) ->
0 = usec_to_seconds(id(1)),
234_567 = usec_to_seconds(id(1_234_567_890*1_000)),
ok.

usec_to_seconds(Usec) when is_integer(Usec) ->
%% The introduction of typed operands caused the loader
%% to incorrectly fuse the following instrutions because
%% the result register ({x,0}) from the 'div' instruction
%% seemed to be distinct from both operands of the 'rem'
%% instruction:
%%
%% {gc_bif,'div',
%% {f,0},
%% 1,
%% [{tr,{x,0},{t_integer,any}},{integer,1000000}],
%% {x,0}}.
%% {gc_bif,'rem',
%% {f,0},
%% 1,
%% [{tr,{x,0},{t_integer,any}},{integer,1000000}],
%% {x,0}}.
Sec = Usec div 1000000,
Sec rem 1000000.

unvalue(V) ->
Abstr = erl_parse:abstract(V),
erl_parse:anno_to_term(Abstr).
Expand Down