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build: add RISC-V native case #7859

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@yskelg yskelg commented Nov 14, 2023

#7498 Add a case for RISC-V native builds.
Future RISC-V JIT development will be utilize added this case.

Add a case for RISC-V native builds.
Future RISC-V JIT development will be utilize added this case.
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@yskelg yskelg changed the title build: Add RISC-V native case build: add RISC-V native case Nov 19, 2023
@IngelaAndin IngelaAndin added the team:VM Assigned to OTP team VM label Nov 20, 2023
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github-actions bot commented Nov 20, 2023

CT Test Results

       5 files     155 suites   49m 22s ⏱️
1 628 tests 1 578 ✔️ 50 💤 0
2 184 runs  2 114 ✔️ 70 💤 0

Results for commit 08bfc42.

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@jhogberg jhogberg self-assigned this Nov 20, 2023
@jhogberg jhogberg added the testing currently being tested, tag is used by OTP internal CI label Nov 20, 2023
@@ -3027,6 +3029,10 @@ AC_DEFUN([LM_HARDWARE_ARCH], [
AC_MSG_RESULT(yes: adjusting ARCH=arm to ARCH=arm64)
ARCH=arm64
;;
riscv64)
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@mikpe mikpe Nov 20, 2023

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This will never match, since the case values are on the form "<arch>-<4-or-8>". Also it's not clear to me that RISC-V needs this kludge. Are there RISC-V systems that report themselves as riscv64 but generate 32-bit code by default, or report themselves as riscv32 but generate 64-bit code by default? If not, then you don't need to touch this bit.

The origin for was operating systems like Solaris that ran on 64-bit hardware but defaulted (at the time at least) to generating 32-bit code.

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Thanks for the code review @mikpe, I'll update the patch to follow your code review! :)

@jhogberg jhogberg removed the testing currently being tested, tag is used by OTP internal CI label Nov 20, 2023
@jhogberg jhogberg added the waiting waiting for changes/input from author label Dec 18, 2023
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5 participants