Alpha build

Revolution EDA Symbol and Schematic Editors

This release is a very early alpha release where the symbol and schematic editors seem to be working with minimal testing. Schematic editor can create Xyce netlists. There is also a very early implementation for python labels in symbols such that a symbol can have a Python label that will be converted to a numerical value. All of this happens inside 'pdk' submodule. This will be separated in due course.
You could use 'analogLib' and 'designs' libraries as a starting point. Their format should be stable at this point, but no guarantees can be given.

To install the software, download reveda.zip file and extract. There is an executable called reveda in this directory. Inside pdk directory, there is a PyLabel demonstration file. You could add other functions to it.

At present, new Revolution EDA currently consists of the following parts:

Main window

The main window includes a Python command terminal and output terminal where warning and error messages are shown. It also has a menu that currently includes a Verilog-A file importer and menu entry for design library browser.

Library Browser

A designer can create, open, rename, copy and delete cells and cellviews using the library browser. Currently, only schematic, symbol, veriloga and layout views are defined. It has a familiar look-and-feel for the most custom IC design engineers.

Symbol Editor

Symbol editor has the usual array of drawing functions such as line, circle, and rectangle. Moreover the symbol pins can be defined to describe the connection points between the circuit and the device. However the most effort has been spent on symbol labels and attributes to create a highly functional design entry system that is functionally equivalent to commercial offerings that cost tens of thousands euros in license fees.

In Revolution EDA, there are three kinds of labels:

1. Normal labels: These are used annotating each instance of on the schematic editor and are not normally used in any other downstream operations, such as netlisting.
2. NLP labels: These labels are used to designate instance parameters using NLP expression syntax. Such labels are typically used for primary instance parameters such as resistor value, device temperature or MOSFET geometry parameters. They can also be used for device numbering or to display parameters common to all instances of a symbol such as model name.
3. Python labels: These labels refer to Python functions typically defined in the process design kit (PDK) files and allow the full power of Python language to be brought in defining derived parameters of the device instances. For example, such label definitions can be used to define the non-linear dependence of a resistor's value on device temperature or behaviour of geometry dependent parameters in a MOSFET.

There is also symbol attributes which define the properties common to all instances of a device. Symbol attributes can be used to inform downstream operations. For example, NLPDeviceFormat attribute is used to create Spice or Xyce netlist lines for the device. modelName attribute is used to set the model name for the device.

A sample symbol editor screenshot is shown below:

Symbol editor is currently functional but not extensively tested. It still lacks some drawing functions such as polylines, triangles and arcs.

Schematic Editor

Schematic editor allows a designer to instantiate symbols from a symbol selection window, place them on the schematic editor, update instance properties if needed, wire them, add schematic pins and netlist the resulting circuit.

Schematic pins are placed to define the locations where the circuit could be connected other circuits as a subcircuit. Revolution EDA can netlist circuit hieararchically:

********************************************************************************
* Revolution EDA CDL Netlist
* Library: designs
* Top Cell Name: higherOrderFilter
* View Name: schematic
* Date: 2022-11-26 14:02:15.400013
********************************************************************************
.GLOBAL gnd!

XI6  net0 VDD INP cascadedFilter
XI7  OUT VDD net0 cascadedFilter
.SUBCKT cascadedFilter  OUT VDD INP  
XI5  OUT net0 VDD net1 commonSourceAmp
XI2  INP net0 out1 highPassFilter
XI3  out1 net0 net1 highPassFilter
.SUBCKT commonSourceAmp  OUT VSS VDD INP  
RI5 VDD OUT R=1k
MI4 OUT INP VSS VSS nmos w=2u l=0.18u nf=2 as=560n m=1
.ENDS commonSourceAmp 
.SUBCKT highPassFilter  INP VSS OUT  
CI4 OUT VSS C=1p
RI2 OUT INP R=1k
.ENDS highPassFilter 
.ENDS cascadedFilter 
.END

The instance properties can be updated using instance properties dialogue. For a Python label, the value would be calculated shown on the schematic if the label is not hidden. Nets also can be individually named. These names would be used during the netlisting of the circuit. If an unnamed net is connected to a schematic pin, it will have the name of that pin, otherwise each net will be assigned a default net name:

The schematic for a simple common source amplifier where as parameter is determined from NMOS device sizes:

Schematics can be annotated using texts, where text font family, style, size, alignment and rotation can be changed.

Verilog-A

Verilog-A is a widely used behavioural hardware description language for analogue circuits. Xyce, the base simulator for Revolution EDA, currently allows the use of a subset of Verilog-A language to be used in module definitions. Xyce creates dynamically linkable modules for these modules during simulations. The integration of Verilog-A modules will significantly enhance the usability of the Revolution EDA and is currently being worked on.

Revolution EDA infrastructure

As mentioned above, Revolution EDA does not use a database to store the design data. Instead, all design data is organised in folders with a two-level hierarchy. At the first level, there are design libraries, that are ordinary folders with an empty reveda.lib file in them. The locations of design libraries and their names are tracked in the design environment using the library editor dialog.

In turn, each design library includes one or more folders, one for each cell, that include various cellview files. Each cellview file is written as a standard JSON text file. We think the use of databases create a single point of failure in saving and retrieving the design data. Use of plain text files also open the possibility of us e of distributed version control systems such as Git, allowing the transfer of modern software project management techniques to integrated circuit design.