RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
esmil · Feb 13, 2022 · d9a4a3d985ace9a7d6edd6f60ed765443f0c8ae5 · d9a4a3d
1 parent 5243663
commit d9a4a3d985ace9a7d6edd6f60ed765443f0c8ae5
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Showing 3 changed files with 4 additions and 2 deletions.
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
@@ -23,6 +23,8 @@ config SOC_STARFIVE
 	bool "StarFive SoCs"
 	select PINCTRL
 	select RESET_CONTROLLER
+	select SIFIVE_L2
+	select SIFIVE_L2_FLUSH
 	select SIFIVE_PLIC
 	help
 	  This enables support for StarFive SoC platform hardware.

diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
@@ -23,7 +23,7 @@ obj-y				+= qcom/
 obj-y				+= renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)	+= rockchip/
 obj-$(CONFIG_SOC_SAMSUNG)	+= samsung/
-obj-$(CONFIG_SOC_SIFIVE)	+= sifive/
+obj-y				+= sifive/
 obj-y				+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-y				+= ti/

diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE
 
 config SIFIVE_L2
 	bool "Sifive L2 Cache controller"