Double I2C read in one transaction skips a clock pulse (#5528)

[TD-er]

See #5528 and the more elaborate description
where @maarten-pennings did all the hard work, but as far as I could see, no PR was made.

I also noticed some code duplication, which I moved to separate functions.

According to this documentation on I2C clock stretching it is not allowed to have some slave keep the clock low during transmission of a byte, only after an ack.
So that's why it is not done in the while loop.
But I wondered if there should be an extra delay between the sequence of pulses and the extra added clock "valey". See my comment in the code.

Have not tested it myself, this is just the long awaited PR.

[Jason2866]

@TD-er Have you seen #6326 ?
We use this PR for our core pre2.6 Tasmota. We have until now NO feedback with issues with.
Could you adapt you PR to this. This I2C saves a lot of iRam!

[TD-er]

Have seen it and indeed it may be useful to base this PR on that one.
I will have a look at it to see how hard it is to do the same based on that branch.

[TD-er]

@Jason2866 See PR #6592

[earlephilhower]

Minor niggle, but in English it is spelled "valley" (two ells).

According to this documentation on I2C clock stretching it is not allowed to have some slave keep the clock low during transmission of a byte, only after an ack.

NXP (spinoff from Philips IIRC) says that clock stretching can be on a bit-by-bit basis, and that's the way it's (theoretically) done w/the existing I2C code in the repo: https://www.nxp.com/docs/en/user-guide/UM10204.pdf

[TD-er]

@earlephilhower In the other PR #6592 I had also changed it into "valley". Noticed the same strange notation :)

It makes more sense to allow clock stretching per bit, so the device can make sure it will be able to handle the stream.
But I wonder if it will then also be able to read if something is addressed to him/her/it or that it may stretch all bits on the bus even when not addressed to that device.
That would be bad for performance of the whole bus and maybe that's the reason it should not stretch the clock during transfers.

[TD-er]

Superseded by #6654