Changes to sync with freechipsproject/rocket-chip@5155eb6

[VaginAY]

Here is changes to synchronize with current chipsalliance/rocket-chip@5155eb6
master branch.

diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
index 361851b..59df15b 100644
--- a/src/main/scala/common/tile.scala
+++ b/src/main/scala/common/tile.scala
@@ -24,6 +24,7 @@ case class BoomTileParams(
     hcfOnUncorrectable: Boolean = false,
     name: Option[String] = Some("tile"),
     hartid: Int = 0,
+    blockerCtrlAddr: Option[BigInt] = None,
     boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
     ) extends TileParams {
   require(icache.isDefined)
diff --git a/src/main/scala/ifu/ScratchpadSlavePort.scala b/src/main/scala/ifu/ScratchpadSlavePort.scala
index 76339a9..02fe0fc 100644
--- a/src/main/scala/ifu/ScratchpadSlavePort.scala
+++ b/src/main/scala/ifu/ScratchpadSlavePort.scala
@@ -6,7 +6,8 @@ import Chisel._
 import Chisel.ImplicitConversions._
 
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.coreplex.CacheBlockBytes
+import freechips.rocketchip.coreplex.{CacheBlockBytes, SystemBusKey}
+import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
@@ -99,9 +100,10 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics:
 trait CanHaveBoomScratchpad extends HasHellaCache with HasBoomICacheFrontend {
   val module: CanHaveBoomScratchpadModule
   val cacheBlockBytes = p(CacheBlockBytes)
+  val masterPortBeatBytes = p(SystemBusKey).beatBytes
 
   val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
-    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics)))
+    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)))
   }
 
   val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntIdentityNode())
@@ -111,13 +113,21 @@ trait CanHaveBoomScratchpad extends HasHellaCache with HasBoomICacheFrontend {
     beu
   }
 
+  val tile_master_blocker =
+    tileParams.blockerCtrlAddr
+      .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
+      .map(bp => LazyModule(new BasicBusBlocker(bp)))
+
+  masterNode := tile_master_blocker.map { _.node := tileBus.node } getOrElse { tileBus.node }
+
   // connect any combination of ITIM, DTIM, and BusErrorUnit
   val slaveNode = TLIdentityNode()
   DisableMonitors { implicit p =>
     val xbarPorts =
       scratch.map(lm => (lm.node, xBytes)) ++
       busErrorUnit.map(lm => (lm.node, xBytes)) ++
-      tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes)))
+      tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes))) ++
+      tile_master_blocker.map( lm => (lm.controlNode, xBytes))
 
     if (xbarPorts.nonEmpty) {
       val xbar = LazyModule(new TLXbar)

And may I ask you to add this to commit?

diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
index f108a69..e2d31a4 100644
--- a/src/main/scala/system/Configs.scala
+++ b/src/main/scala/system/Configs.scala
@@ -24,6 +24,7 @@ class BoomConfig extends Config(new DefaultBoomConfig ++ new WithNBoomCores(1) +
 class SmallBoomConfig extends Config(new WithSmallBooms ++ new DefaultBoomConfig ++ new WithNBoomCores(1) ++ new WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig)
 class MediumBoomConfig extends Config(new WithMediumBooms ++ new DefaultBoomConfig ++ new WithNBoomCores(1) ++ new WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig)
 class MegaBoomConfig extends Config(new WithMegaBooms ++ new DefaultBoomConfig ++ new WithNBoomCores(1) ++ new WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig)
+class jtagMegaBoomConfig extends Config(new WithMegaBooms ++ new DefaultBoomConfig ++ new WithNBoomCores(1) ++ new WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig ++ new WithJtagDTM)

It seems to me there is no need to produce forks for the sake of adding a configuration that can be useful to everyone. Maybe jtagMediumBoomConfig and jtagSmallBoomConfig should be done too.

[ccelio]

Thank you very much!

It seems to me there is no need to produce forks for the sake of adding a configuration that can be useful to everyone. Maybe jtagMediumBoomConfig and jtagSmallBoomConfig should be done too.

Sure, I can add those configurations. Is there an easy set of instructions I can follow to verify that they work? My only concern is having to support a configuration I can't do regression tests on.

[VaginAY]

We are now working on a solution for Cadence Incisive.
SiFive is currently working on a solution in a traditional manner (one of rocket-chip branch).
A simple set of instructions will be presented after the completion of the work of one of the teams :)
This request can also wait.