Add ESP32-C2 support

.github/workflows/push.yml

@@ -93,7 +93,7 @@ jobs:
         # https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/tools/idf-docker-image.html
         # for details.
         idf_ver: ["release-v5.1"]
-        idf_target: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c6", "esp32h2"]
+        idf_target: ["esp32", "esp32s2", "esp32s3", "esp32c2", "esp32c3", "esp32c6", "esp32h2"]
     container: espressif/idf:${{ matrix.idf_ver }}
     steps:
       - name: Check out arduino-esp32 as a component

boards.txt

@@ -30,6 +30,121 @@ menu.LORAWAN_PREAMBLE_LENGTH=LoRaWan Preamble Length
 ### DO NOT PUT BOARDS ABOVE THE OFFICIAL ESPRESSIF BOARDS! ###
 ##############################################################
 
+esp32c2.name=ESP32C2 Dev Module
+esp32c2.hide=true
+
+esp32c2.bootloader.tool=esptool_py
+esp32c2.bootloader.tool.default=esptool_py
+
+esp32c2.upload.tool=esptool_py
+esp32c2.upload.tool.default=esptool_py
+esp32c2.upload.tool.network=esp_ota
+
+esp32c2.upload.maximum_size=1310720
+esp32c2.upload.maximum_data_size=327680
+esp32c2.upload.flags=
+esp32c2.upload.extra_flags=
+esp32c2.upload.use_1200bps_touch=false
+esp32c2.upload.wait_for_upload_port=false
+
+esp32c2.serial.disableDTR=false
+esp32c2.serial.disableRTS=false
+
+esp32c2.build.tarch=riscv32
+esp32c2.build.target=esp
+esp32c2.build.mcu=esp32c2
+esp32c2.build.core=esp32
+esp32c2.build.variant=esp32c2
+esp32c2.build.board=ESP32C2_DEV
+esp32c2.build.bootloader_addr=0x0
+
+esp32c2.build.cdc_on_boot=0
+esp32c2.build.f_cpu=120000000L
+esp32c2.build.flash_size=2MB
+esp32c2.build.flash_freq=60m
+esp32c2.build.flash_mode=qio
+esp32c2.build.boot=qio
+esp32c2.build.partitions=minimal
+esp32c2.build.defines=
+
+esp32c2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c2.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c2.menu.PartitionScheme.default.build.partitions=default
+esp32c2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+esp32c2.menu.FlashMode.qio=QIO
+esp32c2.menu.FlashMode.qio.build.flash_mode=dio
+esp32c2.menu.FlashMode.qio.build.boot=qio
+esp32c2.menu.FlashMode.dio=DIO
+esp32c2.menu.FlashMode.dio.build.flash_mode=dio
+esp32c2.menu.FlashMode.dio.build.boot=dio
+
+esp32c2.menu.FlashFreq.60=60MHz
+esp32c2.menu.FlashFreq.60.build.flash_freq=60m
+esp32c2.menu.FlashFreq.30=30MHz
+esp32c2.menu.FlashFreq.30.build.flash_freq=30m
+
+esp32c2.menu.FlashSize.2M=2MB (16Mb)
+esp32c2.menu.FlashSize.2M.build.flash_size=2MB
+esp32c2.menu.FlashSize.2M.build.partitions=minimal
+esp32c2.menu.FlashSize.4M=4MB (32Mb)
+esp32c2.menu.FlashSize.4M.build.flash_size=4MB
+
+esp32c2.menu.UploadSpeed.921600=921600
+esp32c2.menu.UploadSpeed.921600.upload.speed=921600
+esp32c2.menu.UploadSpeed.115200=115200
+esp32c2.menu.UploadSpeed.115200.upload.speed=115200
+esp32c2.menu.UploadSpeed.256000.windows=256000
+esp32c2.menu.UploadSpeed.256000.upload.speed=256000
+esp32c2.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c2.menu.UploadSpeed.230400=230400
+esp32c2.menu.UploadSpeed.230400.upload.speed=230400
+esp32c2.menu.UploadSpeed.460800.linux=460800
+esp32c2.menu.UploadSpeed.460800.macosx=460800
+esp32c2.menu.UploadSpeed.460800.upload.speed=460800
+esp32c2.menu.UploadSpeed.512000.windows=512000
+esp32c2.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c2.menu.DebugLevel.none=None
+esp32c2.menu.DebugLevel.none.build.code_debug=0
+esp32c2.menu.DebugLevel.error=Error
+esp32c2.menu.DebugLevel.error.build.code_debug=1
+esp32c2.menu.DebugLevel.warn=Warn
+esp32c2.menu.DebugLevel.warn.build.code_debug=2
+esp32c2.menu.DebugLevel.info=Info
+esp32c2.menu.DebugLevel.info.build.code_debug=3
+esp32c2.menu.DebugLevel.debug=Debug
+esp32c2.menu.DebugLevel.debug.build.code_debug=4
+esp32c2.menu.DebugLevel.verbose=Verbose
+esp32c2.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c2.menu.EraseFlash.none=Disabled
+esp32c2.menu.EraseFlash.none.upload.erase_cmd=
+esp32c2.menu.EraseFlash.all=Enabled
+esp32c2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
 esp32h2.name=ESP32H2 Dev Module
 esp32h2.vid.0=0x303a
 esp32h2.pid.0=0x1001

cores/esp32/Esp.cpp

@@ -48,6 +48,9 @@ extern "C" {
 #include "esp32s3/rom/spi_flash.h"
 #include "soc/efuse_reg.h"
 #define ESP_FLASH_IMAGE_BASE 0x0000     // Esp32s3 is located at 0x0000
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x0000     // Esp32c2 is located at 0x0000
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/spi_flash.h"
 #define ESP_FLASH_IMAGE_BASE 0x0000     // Esp32c3 is located at 0x0000
@@ -366,7 +369,7 @@ FlashMode_t EspClass::getFlashChipMode(void)
    #if CONFIG_IDF_TARGET_ESP32S2
    uint32_t spi_ctrl = REG_READ(PERIPHS_SPI_FLASH_CTRL);
    #else
-   #if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
+   #if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
    uint32_t spi_ctrl = REG_READ(DR_REG_SPI0_BASE + 0x8);
    #else
    uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));

cores/esp32/HardwareSerial.h

@@ -118,6 +118,8 @@ typedef enum {
     #define SOC_RX0 (gpio_num_t)3
   #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
     #define SOC_RX0 (gpio_num_t)44
+  #elif CONFIG_IDF_TARGET_ESP32C2
+    #define SOC_RX0 (gpio_num_t)19
   #elif CONFIG_IDF_TARGET_ESP32C3
     #define SOC_RX0 (gpio_num_t)20
   #elif CONFIG_IDF_TARGET_ESP32C6
@@ -132,6 +134,8 @@ typedef enum {
     #define SOC_TX0 (gpio_num_t)1
   #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
     #define SOC_TX0 (gpio_num_t)43
+  #elif CONFIG_IDF_TARGET_ESP32C2
+    #define SOC_TX0 (gpio_num_t)20
   #elif CONFIG_IDF_TARGET_ESP32C3
     #define SOC_TX0 (gpio_num_t)21
   #elif CONFIG_IDF_TARGET_ESP32C6
@@ -149,6 +153,8 @@ typedef enum {
       #define RX1 (gpio_num_t)26
     #elif CONFIG_IDF_TARGET_ESP32S2
       #define RX1 (gpio_num_t)4
+    #elif CONFIG_IDF_TARGET_ESP32C2
+      #define RX1 (gpio_num_t)10
     #elif CONFIG_IDF_TARGET_ESP32C3
       #define RX1 (gpio_num_t)18
     #elif CONFIG_IDF_TARGET_ESP32S3
@@ -165,6 +171,8 @@ typedef enum {
       #define TX1 (gpio_num_t)27
     #elif CONFIG_IDF_TARGET_ESP32S2
       #define TX1 (gpio_num_t)5
+    #elif CONFIG_IDF_TARGET_ESP32C2
+      #define TX1 (gpio_num_t)18
     #elif CONFIG_IDF_TARGET_ESP32C3
       #define TX1 (gpio_num_t)19
     #elif CONFIG_IDF_TARGET_ESP32S3

cores/esp32/esp32-hal-adc.c

@@ -21,6 +21,14 @@
 #include "esp_adc/adc_continuous.h"
 #include "esp_adc/adc_cali_scheme.h"
 
+// ESP32-C2 does not define those two for some reason
+#ifndef SOC_ADC_DIGI_RESULT_BYTES
+#define SOC_ADC_DIGI_RESULT_BYTES               (4)
+#endif
+#ifndef SOC_ADC_DIGI_DATA_BYTES_PER_CONV
+#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
+#endif
+
 static uint8_t __analogAttenuation = ADC_11db;
 static uint8_t __analogWidth = SOC_ADC_RTC_MAX_BITWIDTH; 
 static uint8_t __analogReturnedWidth = SOC_ADC_RTC_MAX_BITWIDTH;

cores/esp32/esp32-hal-cpu.c

@@ -19,7 +19,7 @@
 #include "esp_attr.h"
 #include "esp_log.h"
 #include "soc/rtc.h"
-#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
+#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
 #include "soc/rtc_cntl_reg.h"
 #include "soc/apb_ctrl_reg.h"
 #endif
@@ -38,6 +38,8 @@
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "freertos/xtensa_timer.h"
 #include "esp32s3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C6
@@ -153,7 +155,7 @@ bool removeApbChangeCallback(void * arg, apb_change_cb_t cb){
 }
 
 static uint32_t calculateApb(rtc_cpu_freq_config_t * conf){
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
+#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
 	return APB_CLK_FREQ;
 #else
     if(conf->freq_mhz >= 80){
@@ -228,7 +230,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
     }
     //Make the frequency change
     rtc_clk_cpu_freq_set_config_fast(&conf);
-#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
+#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
     if(capb != apb){
         //Update REF_TICK (uncomment if REF_TICK is different than 1MHz)
         //if(conf.freq_mhz < 80){
@@ -241,7 +243,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
     }
 #endif
     //Update FreeRTOS Tick Divisor
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
 
 #elif CONFIG_IDF_TARGET_ESP32S3
 

cores/esp32/esp32-hal-i2c-slave.c

@@ -168,7 +168,7 @@ static inline void i2c_ll_stretch_clr(i2c_dev_t *hw)
 
 static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
 {
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
+#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
     return hw->sr.slave_addressed;
 #else
     return hw->status_reg.slave_addressed;
@@ -177,7 +177,7 @@ static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
 
 static inline bool i2c_ll_slave_rw(i2c_dev_t *hw)//not exposed by hal_ll
 {
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
+#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
     return hw->sr.slave_rw;
 #else
     return hw->status_reg.slave_rw;

cores/esp32/esp32-hal-matrix.c

@@ -24,6 +24,8 @@
 #include "esp32s2/rom/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32C6

cores/esp32/esp32-hal-misc.c

@@ -29,7 +29,7 @@
 #endif //CONFIG_BT_ENABLED
 #include <sys/time.h>
 #include "soc/rtc.h"
-#if !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
+#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2)
 #include "soc/rtc_cntl_reg.h"
 #include "soc/apb_ctrl_reg.h"
 #endif
@@ -45,6 +45,8 @@
 #include "esp32s2/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C6

cores/esp32/esp32-hal-rgb-led.c

@@ -1,7 +1,10 @@
+#include "soc/soc_caps.h"
+
 #include "esp32-hal-rgb-led.h"
 
 
 void neopixelWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val){
+#if SOC_RMT_SUPPORTED
   rmt_data_t led_data[24];
 
   // Verify if the pin used is RGB_BUILTIN and fix GPIO number
@@ -34,4 +37,7 @@ void neopixelWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue
     }
   }
   rmtWrite(pin, led_data, RMT_SYMBOLS_OF(led_data), RMT_WAIT_FOR_EVER);
+#else
+    log_e("RMT is not supported on " CONFIG_IDF_TARGET);
+#endif /* SOC_RMT_SUPPORTED */
 }