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Merge branch 'feature/etm_support_h2' into 'master'
etm: add basic driver on esp32h2 Closes IDF-6225 See merge request espressif/esp-idf!22246
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| Supported Targets | ESP32-C6 | | ||
| ----------------- | -------- | | ||
| Supported Targets | ESP32-C6 | ESP32-H2 | | ||
| ----------------- | -------- | -------- | |
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/* | ||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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// Note that most of the register operations in this layer are non-atomic operations. | ||
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#pragma once | ||
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#include <stdbool.h> | ||
#include "hal/assert.h" | ||
#include "hal/misc.h" | ||
#include "soc/soc_etm_struct.h" | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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/** | ||
* @brief Enable the clock for ETM module | ||
* | ||
* @param hw ETM register base address | ||
* @param enable true to enable, false to disable | ||
*/ | ||
static inline void etm_ll_enable_clock(soc_etm_dev_t *hw, bool enable) | ||
{ | ||
hw->clk_en.clk_en = enable; | ||
} | ||
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/** | ||
* @brief Enable ETM channel | ||
* | ||
* @param hw ETM register base address | ||
* @param chan Channel ID | ||
*/ | ||
static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan) | ||
{ | ||
if (chan < 32) { | ||
hw->ch_ena_ad0_set.val = 1 << chan; | ||
} else { | ||
hw->ch_ena_ad1_set.val = 1 << (chan - 32); | ||
} | ||
} | ||
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/** | ||
* @brief Disable ETM channel | ||
* | ||
* @param hw ETM register base address | ||
* @param chan Channel ID | ||
*/ | ||
static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan) | ||
{ | ||
if (chan < 32) { | ||
hw->ch_ena_ad0_clr.val = 1 << chan; | ||
} else { | ||
hw->ch_ena_ad1_clr.val = 1 << (chan - 32); | ||
} | ||
} | ||
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/** | ||
* @brief Check whether the ETM channel is enabled or not | ||
* | ||
* @param hw ETM register base address | ||
* @param chan Channel ID | ||
* @return true if the channel is enabled, false otherwise | ||
*/ | ||
static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan) | ||
{ | ||
if (chan < 32) { | ||
return hw->ch_ena_ad0.val & (1 << chan); | ||
} else { | ||
return hw->ch_ena_ad1.val & (1 << (chan - 32)); | ||
} | ||
} | ||
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/** | ||
* @brief Set the input event for the ETM channel | ||
* | ||
* @param hw ETM register base address | ||
* @param chan Channel ID | ||
* @param event Event ID | ||
*/ | ||
static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event) | ||
{ | ||
hw->channel[chan].evt_id.evt_id = event; | ||
} | ||
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/** | ||
* @brief Set the output task for the ETM channel | ||
* | ||
* @param hw ETM register base address | ||
* @param chan Channel ID | ||
* @param task Task ID | ||
*/ | ||
static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task) | ||
{ | ||
hw->channel[chan].task_id.task_id = task; | ||
} | ||
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#ifdef __cplusplus | ||
} | ||
#endif |
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/* | ||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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// Note that most of the register operations in this layer are non-atomic operations. | ||
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#pragma once | ||
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#include <stdbool.h> | ||
#include "hal/assert.h" | ||
#include "hal/misc.h" | ||
#include "soc/gpio_ext_struct.h" | ||
#include "soc/soc_etm_source.h" | ||
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#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch)) | ||
#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch)) | ||
#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch)) | ||
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#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch)) | ||
#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch)) | ||
#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch)) | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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/** | ||
* @brief Set which GPIO to be bounded to the event channel | ||
* | ||
* @param dev Register base address | ||
* @param chan Channel number | ||
* @param gpio_num GPIO number | ||
*/ | ||
static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num) | ||
{ | ||
dev->etm_event_chn_cfg[chan].etm_ch0_event_sel = gpio_num; | ||
} | ||
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/** | ||
* @brief Wether to enable the event channel | ||
* | ||
* @param dev Register base address | ||
* @param chan Channel number | ||
* @param enable True to enable, false to disable | ||
*/ | ||
static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable) | ||
{ | ||
dev->etm_event_chn_cfg[chan].etm_ch0_event_en = enable; | ||
} | ||
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/** | ||
* @brief Set which GPIO to be bounded to the task channel | ||
* | ||
* @note One channel can be bounded to multiple different GPIOs | ||
* | ||
* @param dev Register base address | ||
* @param chan Channel number | ||
* @param gpio_num GPIO number | ||
*/ | ||
static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan) | ||
{ | ||
int g_p = gpio_num / 4; | ||
int g_idx = gpio_num % 4; | ||
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; | ||
reg_val &= ~(0x07 << (g_idx * 8 + 1)); | ||
reg_val |= ((chan & 0x07) << (g_idx * 8 + 1)); | ||
dev->etm_task_pn_cfg[g_p].val = reg_val; | ||
} | ||
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/** | ||
* @brief Wether to enable the GPIO to be managed by the task channel | ||
* | ||
* @param dev Register base address | ||
* @param gpio_num GPIO number | ||
* @param enable True to enable, false to disable | ||
*/ | ||
static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable) | ||
{ | ||
int g_p = gpio_num / 4; | ||
int g_idx = gpio_num % 4; | ||
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val; | ||
reg_val &= ~(0x01 << (g_idx * 8)); | ||
reg_val |= ((enable & 0x01) << (g_idx * 8)); | ||
dev->etm_task_pn_cfg[g_p].val = reg_val; | ||
} | ||
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/** | ||
* @brief Check whether a GPIO has been enabled and managed by a task channel | ||
* | ||
* @param dev Register base address | ||
* @param gpio_num GPIO number | ||
* @return True if enabled, false otherwise | ||
*/ | ||
static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num) | ||
{ | ||
int g_p = gpio_num / 4; | ||
int g_idx = gpio_num % 4; | ||
return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 8)); | ||
} | ||
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/** | ||
* @brief Get the channel number that the GPIO is bounded to | ||
* | ||
* @param dev Register base address | ||
* @param gpio_num GPIO number | ||
* @return GPIO ETM Task channel number | ||
*/ | ||
static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num) | ||
{ | ||
int g_p = gpio_num / 4; | ||
int g_idx = gpio_num % 4; | ||
return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 8 + 1)) & 0x07; | ||
} | ||
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#ifdef __cplusplus | ||
} | ||
#endif |
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