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ulp: refactor ulp component

Closes IDF-4520

See merge request espressif/esp-idf!16886
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sudeep-mohanty committed Jan 28, 2022
2 parents 7f1dc67 + 2fc9bd6 commit 1c393a3
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Showing 68 changed files with 786 additions and 869 deletions.
22 changes: 0 additions & 22 deletions components/esp32/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -500,28 +500,6 @@ menu "ESP32-specific"
default 0x4000 if ESP32_MEMMAP_TRACEMEM && !ESP32_MEMMAP_TRACEMEM_TWOBANKS
default 0x0



config ESP32_ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default "n"
help
Set to 'y' if you plan to load a firmware for the coprocessor.

If this option is enabled, further coprocessor configuration will appear in the Components menu.

config ESP32_ULP_COPROC_RESERVE_MEM
int
prompt "RTC slow memory reserved for coprocessor" if ESP32_ULP_COPROC_ENABLED
default 512 if ESP32_ULP_COPROC_ENABLED
range 32 8176 if ESP32_ULP_COPROC_ENABLED
default 0 if !ESP32_ULP_COPROC_ENABLED
range 0 0 if !ESP32_ULP_COPROC_ENABLED
help
Bytes of memory to reserve for ULP coprocessor firmware & data.

Data is reserved at the beginning of RTC slow memory.

config ESP32_DEBUG_OCDAWARE
bool "Make exception and panic handlers JTAG/OCD aware"
default y
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4 changes: 2 additions & 2 deletions components/esp32/sdkconfig.rename
Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@ CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 CONFIG_ESP32_RTC_CLK_SRC
CONFIG_DISABLE_BASIC_ROM_CONSOLE CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE
CONFIG_NO_BLOBS CONFIG_ESP32_NO_BLOBS
CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS
CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
CONFIG_ESP32_ULP_COPROC_ENABLED CONFIG_ULP_COPROC_ENABLED
CONFIG_ESP32_ULP_COPROC_RESERVE_MEM CONFIG_ULP_COPROC_RESERVE_MEM
CONFIG_BROWNOUT_DET CONFIG_ESP32_BROWNOUT_DET
CONFIG_BROWNOUT_DET_LVL_SEL CONFIG_ESP32_BROWNOUT_DET_LVL_SEL
CONFIG_BROWNOUT_DET_LVL_SEL_0 CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0
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28 changes: 0 additions & 28 deletions components/esp32s2/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -220,34 +220,6 @@ menu "ESP32S2-specific"
default 0x4000 if ESP32S2_MEMMAP_TRACEMEM && !ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
default 0x0


config ESP32S2_ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default "n"
help
Set to 'y' if you plan to load a firmware for the coprocessor.

If this option is enabled, further coprocessor configuration will appear in the Components menu.

config ESP32S2_ULP_COPROC_RESERVE_MEM
int
prompt "RTC slow memory reserved for coprocessor" if ESP32S2_ULP_COPROC_ENABLED
default 2048 if ESP32S2_ULP_COPROC_ENABLED
range 32 8176 if ESP32S2_ULP_COPROC_ENABLED
default 0 if !ESP32S2_ULP_COPROC_ENABLED
range 0 0 if !ESP32S2_ULP_COPROC_ENABLED
help
Bytes of memory to reserve for ULP coprocessor firmware & data.

Data is reserved at the beginning of RTC slow memory.

config ESP32S2_ULP_COPROC_RISCV
bool "Enable RISC-V as ULP coprocessor"
depends on ESP32S2_ULP_COPROC_ENABLED
default n
help
Set this to y to use the RISC-V coprocessor instead of the FSM-ULP.

config ESP32S2_DEBUG_OCDAWARE
bool "Make exception and panic handlers JTAG/OCD aware"
default y
Expand Down
7 changes: 7 additions & 0 deletions components/esp32s2/sdkconfig.rename
Original file line number Diff line number Diff line change
@@ -0,0 +1,7 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION

# ESP32-S2 specific
CONFIG_ESP32S2_ULP_COPROC_ENABLED CONFIG_ULP_COPROC_ENABLED
CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM CONFIG_ULP_COPROC_RESERVE_MEM
CONFIG_ESP32S2_ULP_COPROC_RISCV CONFIG_ULP_COPROC_TYPE_RISCV
28 changes: 0 additions & 28 deletions components/esp32s3/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -306,34 +306,6 @@ menu "ESP32S3-Specific"
default 0x4000 if ESP32S3_MEMMAP_TRACEMEM && !ESP32S3_MEMMAP_TRACEMEM_TWOBANKS
default 0x0


config ESP32S3_ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Coprocessor"
default "n"
help
Set to 'y' if you plan to load a firmware for the coprocessor.

If this option is enabled, further coprocessor configuration will appear in the Components menu.

config ESP32S3_ULP_COPROC_RESERVE_MEM
int
prompt "RTC slow memory reserved for coprocessor" if ESP32S3_ULP_COPROC_ENABLED
default 512 if ESP32S3_ULP_COPROC_ENABLED
range 32 8176 if ESP32S3_ULP_COPROC_ENABLED
default 0 if !ESP32S3_ULP_COPROC_ENABLED
range 0 0 if !ESP32S3_ULP_COPROC_ENABLED
help
Bytes of memory to reserve for ULP coprocessor firmware & data.

Data is reserved at the beginning of RTC slow memory.

config ESP32S3_ULP_COPROC_RISCV
bool "Enable RISC-V as ULP coprocessor"
depends on ESP32S3_ULP_COPROC_ENABLED
default n
help
Set this to y to use the RISC-V coprocessor instead of the FSM-ULP.

config ESP32S3_DEBUG_OCDAWARE
bool "Make exception and panic handlers JTAG/OCD aware"
default y
Expand Down
6 changes: 3 additions & 3 deletions components/esp_common/src/esp_err_to_name.c
Original file line number Diff line number Diff line change
Expand Up @@ -62,8 +62,8 @@
#if __has_include("soc/esp32s2/esp_ds.h")
#include "soc/esp32s2/esp_ds.h"
#endif
#if __has_include("ulp_common.h")
#include "ulp_common.h"
#if __has_include("ulp_fsm_common.h")
#include "ulp_fsm_common.h"
#endif

#ifdef CONFIG_ESP_ERR_TO_NAME_LOOKUP
Expand Down Expand Up @@ -221,7 +221,7 @@ static const esp_err_msg_t esp_err_msg_table[] = {
forbidden since the NVS encryption works
differently. */
# endif
// components/ulp/include/ulp_common.h
// components/ulp/ulp_fsm/include/ulp_fsm_common.h
# ifdef ESP_ERR_ULP_BASE
ERR_TBL_IT(ESP_ERR_ULP_BASE), /* 4608 0x1200 Offset for ULP-related error codes */
# endif
Expand Down
10 changes: 5 additions & 5 deletions components/esp_hw_support/sleep_modes.c
Original file line number Diff line number Diff line change
Expand Up @@ -765,7 +765,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
}
#if defined(CONFIG_ESP32_ULP_COPROC_ENABLED) || defined(CONFIG_ESP32S2_ULP_COPROC_ENABLED) || defined(CONFIG_ESP32S3_ULP_COPROC_ENABLED)
#if CONFIG_ULP_COPROC_ENABLED
else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
}
Expand All @@ -779,21 +779,21 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)

esp_err_t esp_sleep_enable_ulp_wakeup(void)
{
#ifndef CONFIG_ULP_COPROC_ENABLED
return ESP_ERR_INVALID_STATE;
#endif // CONFIG_ULP_COPROC_ENABLED

#if CONFIG_IDF_TARGET_ESP32
#if ((defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2))
ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal");
return ESP_ERR_NOT_SUPPORTED;
#endif
#ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
return ESP_ERR_INVALID_STATE;
}
s_config.wakeup_triggers |= RTC_ULP_TRIG_EN;
return ESP_OK;
#else // CONFIG_ESP32_ULP_COPROC_ENABLED
return ESP_ERR_INVALID_STATE;
#endif // CONFIG_ESP32_ULP_COPROC_ENABLED
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
s_config.wakeup_triggers |= (RTC_ULP_TRIG_EN | RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN);
return ESP_OK;
Expand Down
12 changes: 5 additions & 7 deletions components/esp_pm/test/test_pm.c
Original file line number Diff line number Diff line change
Expand Up @@ -20,13 +20,15 @@

#include "sdkconfig.h"

#if CONFIG_ULP_COPROC_TYPE_FSM
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/ulp.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/ulp.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/ulp.h"
#endif
#endif //CONFIG_ULP_COPROC_TYPE_FSM

TEST_CASE("Can dump power management lock stats", "[pm]")
{
Expand Down Expand Up @@ -174,20 +176,15 @@ TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]")
TEST_ESP_OK(gptimer_del_timer(gptimer));
}

#if CONFIG_ULP_COPROC_TYPE_FSM
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
#if !DISABLED_FOR_TARGETS(ESP32C3)
// No ULP on C3

// Fix failure on ESP32 when running alone; passes when the previous test is run before this one
TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm][ignore]")
{
#if CONFIG_IDF_TARGET_ESP32
assert(CONFIG_ESP32_ULP_COPROC_RESERVE_MEM >= 16 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
#elif CONFIG_IDF_TARGET_ESP32S2
assert(CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM >= 16 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
#elif CONFIG_IDF_TARGET_ESP32S3
assert(CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM >= 16 && "this test needs ESP32_ULP_COPROC_RESERVE_MEM option set in menuconfig");
#endif
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 16 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");

/* Set up GPIO used to wake up RTC */
const int ext1_wakeup_gpio = 25;
Expand Down Expand Up @@ -253,6 +250,7 @@ TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm][ignore]")
}
#endif //!DISABLED_FOR_TARGETS(ESP32C3)
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
#endif //CONFIG_ULP_COPROC_TYPE_FSM

typedef struct {
int delay_us;
Expand Down
8 changes: 6 additions & 2 deletions components/esp_system/ld/esp32/memory.ld.in
Original file line number Diff line number Diff line change
Expand Up @@ -100,8 +100,12 @@ MEMORY

Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
#if CONFIG_ULP_COPROC_ENABLED
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM
#else
rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000
#endif // CONFIG_ULP_COPROC_ENABLED

/* external memory */
extern_ram_seg(RWX) : org = 0x3F800000,
Expand Down
8 changes: 6 additions & 2 deletions components/esp_system/ld/esp32s2/memory.ld.in
Original file line number Diff line number Diff line change
Expand Up @@ -103,8 +103,12 @@ MEMORY

Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
#if CONFIG_ULP_COPROC_ENABLED
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM
#else
rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000
#endif // CONFIG_ULP_COPROC_ENABLED

/* RTC fast memory (same block as above), viewed from data bus */
rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
Expand Down
8 changes: 6 additions & 2 deletions components/esp_system/ld/esp32s3/memory.ld.in
Original file line number Diff line number Diff line change
Expand Up @@ -109,8 +109,12 @@ MEMORY
* RTC slow memory (data accessible). Persists over deep sleep.
* Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
#if CONFIG_ULP_COPROC_ENABLED
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x2000 - CONFIG_ULP_COPROC_RESERVE_MEM
#else
rtc_slow_seg(RW) : org = 0x50000000 , len = 0x2000
#endif // CONFIG_ULP_COPROC_ENABLED
}

#if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE
Expand Down
27 changes: 21 additions & 6 deletions components/ulp/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -1,16 +1,31 @@
idf_build_get_property(target IDF_TARGET)

set(srcs "")
set(includes include)
set(includes "")

if(CONFIG_SOC_ULP_SUPPORTED OR CONFIG_SOC_RISCV_COPROC_SUPPORTED)

if(CONFIG_SOC_ULP_SUPPORTED)
list(APPEND srcs
"ulp.c"
"ulp_macro.c")
"ulp_common/ulp_common.c")

list(APPEND includes
ulp_common/include
ulp_common/include/${target})

if(CONFIG_ULP_COPROC_TYPE_FSM)
list(APPEND srcs
"ulp_fsm/ulp.c"
"ulp_fsm/ulp_macro.c")

list(APPEND includes
ulp_fsm/include)

if(CONFIG_SOC_RISCV_COPROC_SUPPORTED)
elseif(CONFIG_ULP_COPROC_TYPE_RISCV)
list(APPEND srcs
"ulp_riscv.c")
"ulp_riscv/ulp_riscv.c")

list(APPEND includes
ulp_riscv/include)
endif()
endif()

Expand Down
38 changes: 38 additions & 0 deletions components/ulp/Kconfig
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
menu "Ultra Low Power (ULP) Co-processor"
depends on (SOC_ULP_SUPPORTED || SOC_RISCV_COPROC_SUPPORTED)

config ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Co-processor"
default "n"
help
Enable this feature if you plan to use the ULP Co-processor.
Once this option is enabled, further ULP co-processor configuration will appear in the menu.

choice ULP_COPROC_TYPE
prompt "ULP Co-processor type"
depends on ULP_COPROC_ENABLED
default ULP_COPROC_TYPE_FSM if IDF_TARGET_ESP32
default ULP_COPROC_TYPE_RISCV if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
help
Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
Please note that ESP32 only supports ULP FSM.

config ULP_COPROC_TYPE_FSM
bool "ULP FSM (Finite State Machine)"
config ULP_COPROC_TYPE_RISCV
bool "ULP RISC-V"
depends on !IDF_TARGET_ESP32
endchoice

config ULP_COPROC_RESERVE_MEM
int
prompt "RTC slow memory reserved for coprocessor"
depends on ULP_COPROC_ENABLED
default 512 if IDF_TARGET_ESP32
default 4096 if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
range 32 8176
help
Bytes of memory to reserve for ULP Co-processor firmware & data.
Data is reserved at the beginning of RTC slow memory.

endmenu # Ultra Low Power (ULP) Co-processor
11 changes: 6 additions & 5 deletions components/ulp/README.rst
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
Programming ULP coprocessor using C macros (legacy)
===================================================
Programming ULP FSM coprocessor using C macros (legacy)
=======================================================

In addition to the existing binutils port for the ESP32 ULP coprocessor, it is possible to generate programs for the ULP by embedding assembly-like macros into an ESP32 application. Here is an example how this can be done::

Expand Down Expand Up @@ -65,9 +65,10 @@ Header File

.. list::

:esp32: - :component_file:`ulp/include/esp32/ulp.h`
:esp32s2: - :component_file:`ulp/include/esp32s2/ulp.h`
:esp32s3: - :component_file:`ulp/include/esp32s3/ulp.h`
:component_file:`ulp/ulp_fsm/include/ulp_fsm_common.h`
:esp32: - :component_file:`ulp/ulp_fsm/include/esp32/ulp.h`
:esp32s2: - :component_file:`ulp/ulp_fsm/include/esp32s2/ulp.h`
:esp32s3: - :component_file:`ulp/ulp_fsm/include/esp32s3/ulp.h`

Functions
^^^^^^^^^
Expand Down
4 changes: 2 additions & 2 deletions components/ulp/cmake/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -17,10 +17,10 @@ string(REGEX MATCH "\\(GNU Binutils\\) (${version_pattern})" as_version ${as_out
set(as_version ${CMAKE_MATCH_1})


message(STATUS "Building ULP app ${ULP_APP_NAME} for ${IDF_TARGET}")
message(STATUS "Building ULP app ${ULP_APP_NAME}")

if(ULP_COCPU_IS_RISCV)
set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/${IDF_TARGET}.ulp.riscv.ld)
set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/ulp_riscv.ld)
else()
message(STATUS "ULP assembler version: ${as_version}")

Expand Down
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