flash_encryption: Fix issue that flash encryption cannot work when 8-…

…line psram enabled,

                  Closes #9244,
                  Closes #9287

components/hal/esp32s3/include/hal/spimem_flash_ll.h

@@ -495,6 +495,8 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
  */
 static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
 {
+    // set the correct address length here (24-length or 32-length address),
+    dev->cache_fctrl.usr_cmd_4byte = (bitlen == 32) ? 1 : 0 ;
     dev->user1.usr_addr_bitlen = (bitlen - 1);
     dev->user.usr_addr = bitlen ? 1 : 0;
 }

components/spi_flash/flash_ops.c

@@ -914,12 +914,17 @@ void IRAM_ATTR spi_flash_set_rom_required_regs(void)
 #endif
 }
 
+#if CONFIG_SPIRAM_MODE_OCT
+// This function will only be called when Octal PSRAM enabled.
 void IRAM_ATTR spi_flash_set_vendor_required_regs(void)
 {
 #if CONFIG_ESPTOOLPY_OCT_FLASH
     //Flash chip requires MSPI specifically, call this function to set them
     esp_opiflash_set_required_regs();
+    SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 1, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
 #else
-    //currently we don't need to set other MSPI registers for Quad Flash
-#endif
+    // Set back MSPI registers after Octal PSRAM initialization.
+    SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 0, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
+#endif // CONFIG_ESPTOOLPY_OCT_FLASH
 }
+#endif