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Merge branch 'feature/add_esp32c6_esp_system_support' into 'master'
ESP32C6: Add esp_system related support See merge request espressif/esp-idf!19923
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,149 @@ | ||
| /* | ||
| * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
|
|
||
| /** | ||
| * ESP32-C6 Linker Script Memory Layout | ||
| * This file describes the memory layout (memory blocks) by virtual memory addresses. | ||
| * This linker script is passed through the C preprocessor to include configuration options. | ||
| * Please use preprocessor features sparingly! | ||
| * Restrict to simple macros with numeric values, and/or #if/#endif blocks. | ||
| */ | ||
|
|
||
| #include "sdkconfig.h" | ||
| #include "ld.common" | ||
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| #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC | ||
| #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE) | ||
| #elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP) | ||
| #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE) | ||
| #else | ||
| #define ESP_BOOTLOADER_RESERVE_RTC 0 | ||
| #endif | ||
|
|
||
| /** | ||
| * physical memory is mapped twice to the vritual address (IRAM and DRAM). | ||
| * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory | ||
| */ | ||
| #define SRAM_IRAM_START 0x40800000 | ||
| #define SRAM_DRAM_START 0x40800000 | ||
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|
||
| #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) | ||
| #define SRAM_DRAM_END 0x40880000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ | ||
|
|
||
| #define SRAM_IRAM_ORG (SRAM_IRAM_START) | ||
| #define SRAM_DRAM_ORG (SRAM_DRAM_START) | ||
|
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| #define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG | ||
|
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||
| #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
| /* | ||
| * IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB | ||
| */ | ||
| #define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8) | ||
| #endif | ||
|
|
||
| #if CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE | ||
| ASSERT((CONFIG_ESP32C6_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.") | ||
| #define DRAM0_0_SEG_LEN CONFIG_ESP3C6_FIXED_STATIC_RAM_SIZE | ||
| #else | ||
| #define DRAM0_0_SEG_LEN I_D_SRAM_SIZE | ||
| #endif // CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE | ||
| MEMORY | ||
| { | ||
| /** | ||
| * All these values assume the flash cache is on, and have the blocks this uses subtracted from the length | ||
| * of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but | ||
| * are connected to the data port of the CPU and eg allow byte-wise access. | ||
| */ | ||
|
|
||
| /* IRAM for PRO CPU. */ | ||
| iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE | ||
|
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| #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
| /* Flash mapped instruction data */ | ||
| iram0_2_seg (RX) : org = 0x42000020, len = (IDRAM0_2_SEG_SIZE >> 1) -0x20 | ||
|
|
||
| /** | ||
| * (0x20 offset above is a convenience for the app binary image generation. | ||
| * Flash cache has 64KB pages. The .bin file which is flashed to the chip | ||
| * has a 0x18 byte file header, and each segment has a 0x08 byte segment | ||
| * header. Setting this offset makes it simple to meet the flash cache MMU's | ||
| * constraint that (paddr % 64KB == vaddr % 64KB).) | ||
| */ | ||
| #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
|
|
||
| /** | ||
| * Shared data RAM, excluding memory reserved for ROM bss/data/stack. | ||
| * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. | ||
| */ | ||
| dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN | ||
|
|
||
| #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
| /* Flash mapped constant data */ | ||
| drom0_0_seg (R) : org = 0x42000020 + (IDRAM0_2_SEG_SIZE >> 1), len = (IDRAM0_2_SEG_SIZE >> 1)-0x20 | ||
|
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||
| /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ | ||
| #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
|
|
||
| /** | ||
| * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 | ||
| */ | ||
| #if CONFIG_ULP_COPROC_ENABLED | ||
| lp_ram_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM, | ||
| len = 0x4000 - CONFIG_ULP_COPROC_RESERVE_MEM | ||
| #else | ||
| lp_ram_seg(RW) : org = 0x50000000 , len = 0x4000 | ||
| #endif // CONFIG_ULP_COPROC_ENABLED | ||
|
|
||
| } | ||
|
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| #if CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE | ||
| /* static data ends at defined address */ | ||
| _static_data_end = 0x40820000 + DRAM0_0_SEG_LEN; | ||
| #else | ||
| _static_data_end = _bss_end; | ||
| #endif // CONFIG_ESP32C6_USE_FIXED_STATIC_RAM_SIZE | ||
|
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||
| /* Heap ends at top of dram0_0_seg */ | ||
| _heap_end = 0x40000000; | ||
|
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| _data_seg_org = ORIGIN(rtc_data_seg); | ||
|
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||
| /** | ||
| * The lines below define location alias for .rtc.data section | ||
| * C6 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section | ||
| * Thus, the following region segments are not configurable like on other targets | ||
| */ | ||
| REGION_ALIAS("rtc_iram_seg", lp_ram_seg ); | ||
| REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); | ||
| REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); | ||
| REGION_ALIAS("rtc_data_location", rtc_iram_seg ); | ||
|
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| #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
| REGION_ALIAS("default_code_seg", iram0_2_seg); | ||
| #else | ||
| REGION_ALIAS("default_code_seg", iram0_0_seg); | ||
| #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
|
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| #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
| REGION_ALIAS("default_rodata_seg", drom0_0_seg); | ||
| #else | ||
| REGION_ALIAS("default_rodata_seg", dram0_0_seg); | ||
| #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
|
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||
| /** | ||
| * If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must | ||
| * also be first in the segment. | ||
| */ | ||
| #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS | ||
| ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg), | ||
| ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.") | ||
| #endif | ||
|
|
||
| #if CONFIG_ESP_SYSTEM_USE_EH_FRAME | ||
| ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!"); | ||
| ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!"); | ||
| #endif |
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