Merge branch 'feature/further_support_esp32c2_sleep' into 'master'

esp32c2/sleep: further support sleep for esp32c2 with 26MHz XTAL Closes IDF-5544 See merge request espressif/esp-idf!19017
espressif · Aug 8, 2022 · c25c254 · c25c254
2 parents 21db02c + 209cb1f
commit c25c254
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Showing 58 changed files with 234 additions and 169 deletions.
diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c
@@ -42,13 +42,6 @@ __attribute__((weak)) void bootloader_clock_configure(void)
 
     if (esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW || rtc_clk_apb_freq_get() < APB_CLK_FREQ) {
         rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
-#if CONFIG_IDF_TARGET_ESP32
-        clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
-#endif
-#if CONFIG_IDF_TARGET_ESP32C2
-        clk_cfg.xtal_freq = CONFIG_ESP32C2_XTAL_FREQ;
-#endif
-        /* For other chips, there is no XTAL_FREQ choice */
         clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
         clk_cfg.slow_clk_src = rtc_clk_slow_src_get();
         if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) {

diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c
@@ -576,13 +576,13 @@ void ble_rtc_clk_init(void)
     SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
     SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
 
-#ifdef CONFIG_ESP32C2_XTAL_FREQ_26
+#ifdef CONFIG_XTAL_FREQ_26
     // LP_TIMER_CLK_DIV_NUM -> 130
     SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
 #else
     // LP_TIMER_CLK_DIV_NUM -> 250
     SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
-#endif // CONFIG_ESP32C2_XTAL_FREQ_26
+#endif // CONFIG_XTAL_FREQ_26
 
     // MODEM_CLKRST_ETM_CLK_ACTIVE -> 1
     // MODEM_CLKRST_ETM_CLK_SEL -> 0

diff --git a/components/bt/include/esp32c2/include/esp_bt.h b/components/bt/include/esp32c2/include/esp_bt.h
@@ -226,7 +226,7 @@ typedef struct {
     .coex_phy_coded_tx_rx_time_limit = DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF,     \
     .dis_scan_backoff           = NIMBLE_DISABLE_SCAN_BACKOFF,                          \
     .ble_scan_classify_filter_enable         = 0,                                       \
-    .main_xtal_freq             = CONFIG_ESP32C2_XTAL_FREQ,                             \
+    .main_xtal_freq             = CONFIG_XTAL_FREQ,                                     \
     .config_magic = CONFIG_MAGIC,                                                       \
 };
 

diff --git a/components/bt/include/esp32c2/include/esp_bt_cfg.h b/components/bt/include/esp32c2/include/esp_bt_cfg.h
@@ -192,11 +192,11 @@ extern "C" {
 
 #define BLE_LL_CONN_DEF_AUTH_PYLD_TMO_N     (3000)
 
-#ifdef CONFIG_ESP32C2_XTAL_FREQ_26
+#ifdef CONFIG_XTAL_FREQ_26
     #define RTC_FREQ_N                      (40000) /* in Hz */
 #else
     #define RTC_FREQ_N                      (32000) /* in Hz */
-#endif // CONFIG_ESP32C2_XTAL_FREQ_26
+#endif // CONFIG_XTAL_FREQ_26
 
 #define BLE_LL_TX_PWR_DBM_N                 (0)
 

diff --git a/components/driver/test_apps/gptimer/sdkconfig.ci.esp32c2_xtal26m b/components/driver/test_apps/gptimer/sdkconfig.ci.esp32c2_xtal26m
@@ -1,2 +1,2 @@
 CONFIG_IDF_TARGET="esp32c2"
-CONFIG_ESP32C2_XTAL_FREQ_26=y
+CONFIG_XTAL_FREQ_26=y
diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig
@@ -103,7 +103,6 @@ menu "Hardware Settings"
 
                 If you are seeing "flash read err, 1000" message printed to the
                 console after deep sleep reset, try increasing this value.
-
     endmenu
 
     menu "RTC Clock Config"
@@ -168,7 +167,6 @@ menu "Hardware Settings"
             default 0x4000 if MMU_PAGE_SIZE_16KB
             default 0x8000 if MMU_PAGE_SIZE_32KB
             default 0x10000 if MMU_PAGE_SIZE_64KB
-
     endmenu
 
     # Insert chip-specific HW config
@@ -193,4 +191,45 @@ menu "Hardware Settings"
                 (e.g. SPI Flash write).
     endmenu # GDMA Configuration
 
+    menu "Main XTAL Config"
+        choice XTAL_FREQ_SEL
+            prompt "Main XTAL frequency"
+            default XTAL_FREQ_40 if SOC_XTAL_SUPPORT_40M
+            help
+                This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target.
+                The selected value MUST reflect the frequency of the given hardware.
+
+                Note: The XTAL_FREQ_AUTO option allows the ESP target to automatically estimating XTAL clock's
+                operating frequency. However, this feature is only supported on the ESP32. The ESP32 uses the
+                internal 8MHZ as a reference when estimating. Due to the internal oscillator's frequency being
+                temperature dependent, usage of the XTAL_FREQ_AUTO is not recommended in applications that operate
+                in high ambient temperatures or use high-temperature qualified chips and modules.
+
+            config XTAL_FREQ_24
+                depends on SOC_XTAL_SUPPORT_24M
+                bool "24 MHz"
+            config XTAL_FREQ_26
+                depends on SOC_XTAL_SUPPORT_26M
+                bool "26 MHz"
+            config XTAL_FREQ_32
+                depends on SOC_XTAL_SUPPORT_32M
+                bool "32 MHz"
+            config XTAL_FREQ_40
+                depends on SOC_XTAL_SUPPORT_40M
+                bool "40 MHz"
+            config XTAL_FREQ_AUTO
+                depends on SOC_XTAL_SUPPORT_AUTO_DETECT
+                bool "Autodetect"
+        endchoice
+
+        # rtc_xtal_freq_t enum in soc/rtc.h lists the XTAL frequencies can be supported
+        # SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported
+        config XTAL_FREQ
+            int
+            default 24 if XTAL_FREQ_24
+            default 26 if XTAL_FREQ_26
+            default 32 if XTAL_FREQ_32
+            default 40 if XTAL_FREQ_40
+            default 0  if XTAL_FREQ_AUTO
+    endmenu
 endmenu
diff --git a/components/esp_hw_support/include/esp_private/esp_clk.h b/components/esp_hw_support/include/esp_private/esp_clk.h
@@ -63,7 +63,7 @@ int esp_clk_apb_freq(void);
  * @brief Return frequency of the main XTAL
  *
  * Frequency of the main XTAL can be either auto-detected or set at compile
- * time (see CONFIG_ESP32_XTAL_FREQ_SEL sdkconfig option). In both cases, this
+ * time (see CONFIG_XTAL_FREQ_SEL sdkconfig option). In both cases, this
  * function returns the actual value at run time.
  *
  * @return XTAL frequency, in Hz

diff --git a/components/esp_hw_support/port/esp32/Kconfig.hw_support b/components/esp_hw_support/port/esp32/Kconfig.hw_support
@@ -24,33 +24,3 @@ config ESP32_REV_MIN
     default 1 if ESP32_REV_MIN_1
     default 2 if ESP32_REV_MIN_2
     default 3 if ESP32_REV_MIN_3
-
-choice ESP32_XTAL_FREQ_SEL
-    prompt "Main XTAL frequency"
-    default ESP32_XTAL_FREQ_40
-    help
-        ESP32 currently supports the following XTAL frequencies:
-
-        - 26 MHz
-        - 40 MHz
-
-        Startup code can automatically estimate XTAL frequency. This feature
-        uses the internal 8MHz oscillator as a reference. Because the internal
-        oscillator frequency is temperature dependent, it is not recommended
-        to use automatic XTAL frequency detection in applications which need
-        to work at high ambient temperatures and use high-temperature
-        qualified chips and modules.
-    config ESP32_XTAL_FREQ_40
-        bool "40 MHz"
-    config ESP32_XTAL_FREQ_26
-        bool "26 MHz"
-    config ESP32_XTAL_FREQ_AUTO
-        bool "Autodetect"
-endchoice
-
-# Keep these values in sync with rtc_xtal_freq_t enum in soc/rtc.h
-config ESP32_XTAL_FREQ
-    int
-    default 0 if ESP32_XTAL_FREQ_AUTO
-    default 40 if ESP32_XTAL_FREQ_40
-    default 26 if ESP32_XTAL_FREQ_26
diff --git a/components/esp_hw_support/port/esp32/rtc_clk_init.c b/components/esp_hw_support/port/esp32/rtc_clk_init.c
@@ -95,7 +95,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
 
         rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
         if (est_xtal_freq != configured_xtal_freq) {
-            ESP_HW_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
+            ESP_HW_LOGW(TAG, "Possibly invalid CONFIG_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
                     configured_xtal_freq, est_xtal_freq);
         }
     }

diff --git a/components/esp_hw_support/port/esp32c2/Kconfig.hw_support b/components/esp_hw_support/port/esp32c2/Kconfig.hw_support
diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c
@@ -302,8 +302,8 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
 {
     uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
     if (xtal_freq_mhz == 0) {
-        ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_ESP32C2_XTAL_FREQ);
-        return CONFIG_ESP32C2_XTAL_FREQ;
+        ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_XTAL_FREQ);
+        return CONFIG_XTAL_FREQ;
     }
     return (rtc_xtal_freq_t)xtal_freq_mhz;
 }

diff --git a/components/esp_hw_support/port/esp32c2/systimer.c b/components/esp_hw_support/port/esp32c2/systimer.c
@@ -12,7 +12,7 @@
  *        So the resolution of the systimer is 40MHz/2.5 = 16MHz, or 26MHz/2.5 = 10.4MHz.
  */
 
-#if CONFIG_ESP32C2_XTAL_FREQ_40
+#if CONFIG_XTAL_FREQ_40
 uint64_t systimer_ticks_to_us(uint64_t ticks)
 {
     return ticks / 16;
@@ -22,7 +22,7 @@ uint64_t systimer_us_to_ticks(uint64_t us)
 {
     return us * 16;
 }
-#elif CONFIG_ESP32C2_XTAL_FREQ_26
+#elif CONFIG_XTAL_FREQ_26
 uint64_t systimer_ticks_to_us(uint64_t ticks)
 {
     return ticks * 5 / 52;
@@ -34,4 +34,4 @@ uint64_t systimer_us_to_ticks(uint64_t us)
 }
 #else
 #error "Unsupported XTAL frequency by systimer"
-#endif // CONFIG_ESP32C2_XTAL_FREQ_xx
+#endif // CONFIG_XTAL_FREQ_xx
diff --git a/components/esp_hw_support/sdkconfig.rename.esp32 b/components/esp_hw_support/sdkconfig.rename.esp32
@@ -22,3 +22,8 @@ CONFIG_ESP32_SPIRAM_SUPPORT                             CONFIG_SPIRAM
 CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST           CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP
 
 CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY                    CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY
+
+CONFIG_ESP32_XTAL_FREQ_26                               CONFIG_XTAL_FREQ_26
+CONFIG_ESP32_XTAL_FREQ_40                               CONFIG_XTAL_FREQ_40
+CONFIG_ESP32_XTAL_FREQ_AUTO                             CONFIG_XTAL_FREQ_AUTO
+CONFIG_ESP32_XTAL_FREQ                                  CONFIG_XTAL_FREQ
diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
@@ -331,7 +331,7 @@ menu "ESP System Settings"
         int
         prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
         depends on ESP_CONSOLE_UART
-        default 74880 if ESP32C2_XTAL_FREQ_26
+        default 74880 if (IDF_TARGET_ESP32C2 && XTAL_FREQ_26)
         default 115200
         range 1200 4000000 if !PM_ENABLE
         range 1200 1000000 if PM_ENABLE

diff --git a/components/esp_system/port/soc/esp32c2/clk.c b/components/esp_system/port/soc/esp32c2/clk.c
@@ -71,7 +71,9 @@ static const char *TAG = "clk";
     }
     rtc_init(cfg);
 
-    assert(rtc_clk_xtal_freq_get() == CONFIG_ESP32C2_XTAL_FREQ);
+#ifndef CONFIG_XTAL_FREQ_AUTO
+    assert(rtc_clk_xtal_freq_get() == CONFIG_XTAL_FREQ);
+#endif
 
     bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
     rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);

diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -127,6 +127,18 @@ config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL
     int
     default 5
 
+config SOC_XTAL_SUPPORT_26M
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_40M
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_AUTO_DETECT
+    bool
+    default y
+
 config SOC_ADC_RTC_CTRL_SUPPORTED
     bool
     default y

diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h
@@ -122,7 +122,7 @@ typedef struct rtc_clk_config_s {
  * Default initializer for rtc_clk_config_t
  */
 #define RTC_CLK_CONFIG_DEFAULT() { \
-    .xtal_freq = RTC_XTAL_FREQ_AUTO, \
+    .xtal_freq = CONFIG_XTAL_FREQ, \
     .cpu_freq_mhz = 80, \
     .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
     .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \

diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
@@ -96,6 +96,11 @@
 #endif // SOC_CAPS_ECO_VER < 2
 #define SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL (5U)
 
+/*-------------------------- XTAL CAPS ---------------------------------------*/
+#define SOC_XTAL_SUPPORT_26M            1
+#define SOC_XTAL_SUPPORT_40M            1
+#define SOC_XTAL_SUPPORT_AUTO_DETECT    1
+
 /*-------------------------- ADC CAPS ----------------------------------------*/
 /*!< SAR ADC Module*/
 #define SOC_ADC_RTC_CTRL_SUPPORTED              1

diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -67,6 +67,14 @@ config SOC_SYSTIMER_SUPPORTED
     bool
     default y
 
+config SOC_XTAL_SUPPORT_26M
+    bool
+    default y
+
+config SOC_XTAL_SUPPORT_40M
+    bool
+    default y
+
 config SOC_ADC_DIG_CTRL_SUPPORTED
     bool
     default y

diff --git a/components/soc/esp32c2/include/soc/rtc.h b/components/soc/esp32c2/include/soc/rtc.h
@@ -174,7 +174,7 @@ typedef struct {
  * Default initializer for rtc_clk_config_t
  */
 #define RTC_CLK_CONFIG_DEFAULT() { \
-    .xtal_freq = RTC_XTAL_FREQ_40M, \
+    .xtal_freq = CONFIG_XTAL_FREQ, \
     .cpu_freq_mhz = 80, \
     .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
     .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \

diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -42,6 +42,10 @@
 #define SOC_SECURE_BOOT_SUPPORTED       1
 #define SOC_SYSTIMER_SUPPORTED          1
 
+/*-------------------------- XTAL CAPS ---------------------------------------*/
+#define SOC_XTAL_SUPPORT_26M            1
+#define SOC_XTAL_SUPPORT_40M            1
+
 /*-------------------------- ADC CAPS -------------------------------*/
 /*!< SAR ADC Module*/
 #define SOC_ADC_DIG_CTRL_SUPPORTED              1

diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -115,6 +115,10 @@ config SOC_MEMPROT_SUPPORTED
     bool
     default y
 
+config SOC_XTAL_SUPPORT_40M
+    bool
+    default y
+
 config SOC_AES_SUPPORT_DMA
     bool
     default y

diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h
@@ -177,7 +177,7 @@ typedef struct {
  * Default initializer for rtc_clk_config_t
  */
 #define RTC_CLK_CONFIG_DEFAULT() { \
-    .xtal_freq = RTC_XTAL_FREQ_40M, \
+    .xtal_freq = CONFIG_XTAL_FREQ, \
     .cpu_freq_mhz = 80, \
     .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
     .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \

diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -57,6 +57,9 @@
 #define SOC_SECURE_BOOT_SUPPORTED       1
 #define SOC_MEMPROT_SUPPORTED           1
 
+/*-------------------------- XTAL CAPS ---------------------------------------*/
+#define SOC_XTAL_SUPPORT_40M            1
+
 /*-------------------------- AES CAPS -----------------------------------------*/
 #define SOC_AES_SUPPORT_DMA     (1)
 

diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -103,6 +103,10 @@ config SOC_SECURE_BOOT_SUPPORTED
     bool
     default y
 
+config SOC_XTAL_SUPPORT_32M
+    bool
+    default y
+
 config SOC_AES_SUPPORT_DMA
     bool
     default y

diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h
@@ -182,7 +182,7 @@ typedef struct {
  * Default initializer for rtc_clk_config_t
  */
 #define RTC_CLK_CONFIG_DEFAULT() { \
-    .xtal_freq = RTC_XTAL_FREQ_32M, \
+    .xtal_freq = CONFIG_XTAL_FREQ, \
     .cpu_freq_mhz = 32, \
     .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
     .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \

diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -59,6 +59,8 @@
 #define SOC_FLASH_ENC_SUPPORTED         1
 #define SOC_SECURE_BOOT_SUPPORTED       1
 
+/*-------------------------- XTAL CAPS ---------------------------------------*/
+#define SOC_XTAL_SUPPORT_32M            1
 
 /*-------------------------- AES CAPS -----------------------------------------*/
 #define SOC_AES_SUPPORT_DMA     (1)