Merge branch 'bugfix/hpm_dc_default_disabled_v5.1' into 'release/v5.1'

spi_flash: fixed issue that enabling HPM-DC by default may cause app unable to restart (v5.1)

See merge request espressif/esp-idf!26656

components/bootloader/Kconfig.projbuild

@@ -62,34 +62,66 @@ menu "Bootloader config"
         default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
         default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
 
-    config BOOTLOADER_SPI_CUSTOM_WP_PIN
-        bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)"
-        depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
-        default y if BOOTLOADER_SPI_WP_PIN != 7  # backwards compatibility, can remove in IDF 5
-        default n
-        help
-            This setting is only used if the SPI flash pins have been overridden by setting the eFuses
-            SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT.
-
-            When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
-            ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used
-            for external SPIRAM if it is enabled.
-
-            If this config item is set to N (default), the correct WP pin will be automatically used for any
-            Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to
-            Y and specify the GPIO number connected to the WP.
-
-    config BOOTLOADER_SPI_WP_PIN
-        int "Custom SPI Flash WP Pin"
-        range 0 33
-        default 7
-        depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
-        #depends on BOOTLOADER_SPI_CUSTOM_WP_PIN  # backwards compatibility, can uncomment in IDF 5
-        help
-            The option "Use custom SPI Flash WP Pin" must be set or this value is ignored
+    menu "Serial Flash Configurations"
+        config BOOTLOADER_SPI_CUSTOM_WP_PIN
+            bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)"
+            depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
+            default y if BOOTLOADER_SPI_WP_PIN != 7  # backwards compatibility, can remove in IDF 5
+            default n
+            help
+                This setting is only used if the SPI flash pins have been overridden by setting the eFuses
+                SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT.
+
+                When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
+                ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used
+                for external SPIRAM if it is enabled.
+
+                If this config item is set to N (default), the correct WP pin will be automatically used for any
+                Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to
+                Y and specify the GPIO number connected to the WP.
+
+        config BOOTLOADER_SPI_WP_PIN
+            int "Custom SPI Flash WP Pin"
+            range 0 33
+            default 7
+            depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
+            #depends on BOOTLOADER_SPI_CUSTOM_WP_PIN  # backwards compatibility, can uncomment in IDF 5
+            help
+                The option "Use custom SPI Flash WP Pin" must be set or this value is ignored
+
+                If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this
+                value to the GPIO number of the SPI flash WP pin.
+
+        config BOOTLOADER_FLASH_DC_AWARE
+            bool "Allow app adjust Dummy Cycle bits in SPI Flash for higher frequency (READ HELP FIRST)"
+            help
+                This will force 2nd bootloader to be loaded by DOUT mode, and will restore Dummy Cycle setting by
+                resetting the Flash
+
+        config BOOTLOADER_FLASH_XMC_SUPPORT
+            bool "Enable the support for flash chips of XMC (READ DOCS FIRST)"
+            default y
+            help
+                Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
+                XMC chips will be forbidden to be used, when this option is disabled.
 
-            If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this
-            value to the GPIO number of the SPI flash WP pin.
+                DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING.
+
+                comment "Features below require specific hardware (READ DOCS FIRST!)"
+
+        config BOOTLOADER_FLASH_32BIT_ADDR
+            bool
+            default y if ESPTOOLPY_FLASHSIZE_32MB || ESPTOOLPY_FLASHSIZE_64MB || ESPTOOLPY_FLASHSIZE_128MB
+            default n
+            help
+                This is a helper config for 32bits address flash. Invisible for users.
+
+        config BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
+            bool
+            default y if ESPTOOLPY_OCT_FLASH && BOOTLOADER_FLASH_32BIT_ADDR
+            default n
+
+    endmenu
 
     choice BOOTLOADER_VDDSDIO_BOOST
         bool "VDDSDIO LDO voltage"
@@ -439,15 +471,6 @@ menu "Bootloader config"
             - "Reserve RTC FAST memory for custom purposes"
             - "GPIO triggers factory reset"
 
-    config BOOTLOADER_FLASH_XMC_SUPPORT
-        bool "Enable the support for flash chips of XMC (READ HELP FIRST)"
-        default y
-        help
-            Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
-            XMC chips will be forbidden to be used, when this option is disabled.
-
-            DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING.
-
 endmenu  # Bootloader
 
 

components/bootloader/sdkconfig.rename

@@ -23,3 +23,5 @@ CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE         CONFIG_SECURE_FLASH_
 
 # Secure Boot Scheme
 CONFIG_SECURE_BOOT_ENABLED                                  CONFIG_SECURE_BOOT_V1_ENABLED
+
+CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE                    CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH

components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h

@@ -109,7 +109,7 @@ extern const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_sup
   */
 esp_err_t __attribute__((weak)) bootloader_flash_unlock(void);
 
-#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
 /**
  * @brief Enable 32bits address flash(larger than 16MB) can map to cache.
  *

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -413,7 +413,7 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
     return spi_to_esp_err(rc);
 }
 
-#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
 void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode)
 {
     esp_rom_opiflash_spi0rd_t cache_rd = {};

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c

@@ -260,7 +260,7 @@ esp_err_t bootloader_init_spi_flash(void)
     }
 #endif
 
-#if CONFIG_SPI_FLASH_HPM_ENABLE
+#if CONFIG_BOOTLOADER_FLASH_DC_AWARE
     // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot.
     bootloader_spi_flash_reset();
 #endif
@@ -272,7 +272,7 @@ esp_err_t bootloader_init_spi_flash(void)
         bootloader_enable_qio_mode();
     }
 #endif
-#if CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
     bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
 #endif
     print_flash_info(&bootloader_image_hdr);

components/esp_hw_support/port/esp32s3/mspi_timing_config.c

@@ -118,8 +118,8 @@ static uint32_t spi_timing_config_get_dummy(void)
         abort();
     }
 
-#if CONFIG_SPI_FLASH_HPM_ENABLE
-    if (spi_flash_hpm_dummy_adjust()) { // HPM is enabled
+#if CONFIG_SPI_FLASH_HPM_DC_ON
+    if (spi_flash_hpm_dummy_adjust()) { // HPM-DC is enabled
         const spi_flash_hpm_dummy_conf_t *hpm_dummy = spi_flash_hpm_get_dummy();
         switch (mode) {
             case MSPI_TIMING_LL_FLASH_QIO_MODE:
@@ -139,7 +139,7 @@ static uint32_t spi_timing_config_get_dummy(void)
         }
     } else
 #endif
-    { // HPM is not enabled
+    { // HPM-DC is not enabled
         switch (mode) {
             case MSPI_TIMING_LL_FLASH_QIO_MODE:
                 return SPI1_R_QIO_DUMMY_CYCLELEN;

components/esp_hw_support/test_apps/mspi/sdkconfig.ci.f4r4_120sdr

@@ -3,5 +3,7 @@
 CONFIG_PARTITION_TABLE_CUSTOM=y
 CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
 CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_SPI_FLASH_HPM_ENA=y
 CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
 CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y

components/esp_hw_support/test_apps/mspi/sdkconfig.ci.f4r4_120sdr_120sdr

@@ -3,7 +3,9 @@
 CONFIG_PARTITION_TABLE_CUSTOM=y
 CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
 CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_SPI_FLASH_HPM_ENA=y
 CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
 CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_SPEED_120M=y

components/esp_hw_support/test_apps/mspi/sdkconfig.ci.f4r4_120sdr_40sdr

@@ -3,7 +3,9 @@
 CONFIG_PARTITION_TABLE_CUSTOM=y
 CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
 CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_SPI_FLASH_HPM_ENA=y
 CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
 CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_SPEED_40M=y

components/esp_hw_support/test_apps/mspi/sdkconfig.ci.f4r4_120sdr_os_silent

@@ -7,5 +7,7 @@ CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
 CONFIG_PARTITION_TABLE_CUSTOM=y
 CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
 CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_SPI_FLASH_HPM_ENA=y
 CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
 CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y

components/esp_hw_support/test_apps/mspi/sdkconfig.ci.f4r8_120sdr

@@ -3,5 +3,7 @@
 CONFIG_PARTITION_TABLE_CUSTOM=y
 CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
 CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_SPI_FLASH_HPM_ENA=y
 CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
 CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y

components/esp_psram/esp32s3/Kconfig.spiram

@@ -83,7 +83,7 @@ menu "SPI RAM config"
 
         config SPIRAM_SPEED_120M
             depends on SPIRAM_MODE_QUAD || IDF_EXPERIMENTAL_FEATURES
-            bool "120MHz clock speed"
+            bool "120MHz clock speed (READ DOCS FIRST)"
 
             help
                 - Quad PSRAM 120 MHz is stable.

components/esptool_py/Kconfig.projbuild

@@ -27,8 +27,10 @@ menu "Serial flasher config"
                mode to "OPI" and the sample mode will be STR.
             2. If the flash chip is a Quad one, even if "OPI" is selected in `ESPTOOLPY_FLASHMODE`, our code will
                automatically change the mode to "DIO".
-            3. Please do not rely on this option when you are pretty sure that you are using Octal flash,
-               please enable `ESPTOOLPY_OCT_FLASH` option, then you can choose `DTR` sample mode
+            3. This option is mainly to improve the out-of-box experience of developers. It doesn't guarantee
+               the feature-complete. Some code still rely on `ESPTOOLPY_OCT_FLASH`. Please do not rely on this option
+               when you are pretty sure that you are using Octal flash.
+               In this case, please enable `ESPTOOLPY_OCT_FLASH` option, then you can choose `DTR` sample mode
                in `ESPTOOLPY_FLASH_SAMPLE_MODE`. Otherwise, only `STR` mode is available.
             4. Enabling this feature reduces available internal RAM size (around 900 bytes).
                If your IRAM space is insufficient and you're aware of your flash type,
@@ -92,11 +94,12 @@ menu "Serial flasher config"
         default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
         default ESPTOOLPY_FLASHFREQ_60M if IDF_TARGET_ESP32C2
         config ESPTOOLPY_FLASHFREQ_120M
-            bool "120 MHz"
-            select SPI_FLASH_HPM_ENABLE
+            bool "120 MHz (READ DOCS FIRST)"
             depends on SOC_MEMSPI_SRC_FREQ_120M && \
+                (SPI_FLASH_HPM_ON || ESPTOOLPY_OCT_FLASH) && \
                 (ESPTOOLPY_FLASH_SAMPLE_MODE_STR || IDF_EXPERIMENTAL_FEATURES)
             help
+                - Optional feature for QSPI Flash. Read docs and enable `CONFIG_SPI_FLASH_HPM_ENA` first!
                 - Flash 120 MHz SDR mode is stable.
                 - Flash 120 MHz DDR mode is an experimental feature, it works when
                   the temperature is stable.

components/esptool_py/project_include.cmake

@@ -14,7 +14,7 @@ set(ESPMONITOR ${python} -m esp_idf_monitor)
 set(ESPTOOLPY_CHIP "${chip_model}")
 
 if(NOT CONFIG_APP_BUILD_TYPE_RAM AND CONFIG_APP_BUILD_GENERATE_BINARIES)
-    if(CONFIG_SPI_FLASH_HPM_ENABLE)
+    if(CONFIG_BOOTLOADER_FLASH_DC_AWARE)
     # When set flash frequency to 120M, must keep 1st bootloader work under ``DOUT`` mode
     # because on some flash chips, 120M will modify the status register,
     # which will make ROM won't work.

components/spi_flash/CMakeLists.txt

@@ -13,7 +13,7 @@ else()
         list(APPEND srcs "${target}/spi_flash_oct_flash_init.c")
     endif()
 
-    if(CONFIG_IDF_TARGET_ESP32S3)
+    if(CONFIG_SPI_FLASH_HPM_ON)
         list(APPEND srcs
             "spi_flash_hpm_enable.c")
     endif()