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ulp: added basic support for building and running a binary in the lp core

Closes IDF-6829 and IDF-6272

See merge request espressif/esp-idf!22554
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ESP-Marius committed Mar 10, 2023
2 parents 1f05281 + 284dabf commit dfedaa2
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Showing 33 changed files with 517 additions and 23 deletions.
4 changes: 3 additions & 1 deletion components/esp_hw_support/sleep_modes.c
Original file line number Diff line number Diff line change
Expand Up @@ -483,6 +483,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
}
#endif

#if !CONFIG_IDF_TARGET_ESP32C6 // TODO IDF-7012 Add sleep support for lp core
#if CONFIG_ULP_COPROC_ENABLED
// Enable ULP wakeup
if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) {
Expand All @@ -493,6 +494,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
#endif
}
#endif
#endif //!CONFIG_IDF_TARGET_ESP32C6

if (!deep_sleep) {
misc_modules_sleep_prepare();
Expand Down Expand Up @@ -1000,7 +1002,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
}
#if CONFIG_ULP_COPROC_ENABLED
#if CONFIG_ULP_COPROC_ENABLED && !CONFIG_IDF_TARGET_ESP32C6 // TODO IDF-7012 Add sleep support for lp core
else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
}
Expand Down
5 changes: 0 additions & 5 deletions components/esp_system/ld/esp32h2/memory.ld.in
Original file line number Diff line number Diff line change
Expand Up @@ -91,12 +91,7 @@ MEMORY
/**
* lp ram memory (RWX). Persists over deep sleep. // ESP32H2-TODO IDF-6272
*/
#if CONFIG_ULP_COPROC_ENABLED
lp_ram_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
#else
lp_ram_seg(RW) : org = 0x50000000 , len = 0x1000
#endif // CONFIG_ULP_COPROC_ENABLED

}

Expand Down
4 changes: 4 additions & 0 deletions components/soc/esp32/include/soc/Kconfig.soc_caps.in
Original file line number Diff line number Diff line change
Expand Up @@ -143,6 +143,10 @@ config SOC_BOD_SUPPORTED
bool
default y

config SOC_ULP_FSM_SUPPORTED
bool
default y

config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL
int
default 5
Expand Down
1 change: 1 addition & 0 deletions components/soc/esp32/include/soc/soc_caps.h
Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,7 @@
#define SOC_SECURE_BOOT_SUPPORTED 1
#define SOC_TOUCH_SENSOR_SUPPORTED 1
#define SOC_BOD_SUPPORTED 1
#define SOC_ULP_FSM_SUPPORTED 1

#if SOC_CAPS_ECO_VER < 200
#define SOC_DPORT_WORKAROUND 1
Expand Down
4 changes: 4 additions & 0 deletions components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,10 @@ config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y

config SOC_LP_CORE_SUPPORTED
bool
default y

config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
Expand Down
2 changes: 1 addition & 1 deletion components/soc/esp32c6/include/soc/soc_caps.h
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_WIFI_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
//#define SOC_RISCV_COPROC_SUPPORTED 1 // TODO: IDF-5816
#define SOC_LP_CORE_SUPPORTED 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
Expand Down
1 change: 0 additions & 1 deletion components/soc/esp32h2/include/soc/soc_caps.h
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,6 @@
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
//#define SOC_RISCV_COPROC_SUPPORTED 1 // TODO: IDF-6272
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
Expand Down
4 changes: 4 additions & 0 deletions components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,10 @@ config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y

config SOC_ULP_FSM_SUPPORTED
bool
default y

config SOC_RISCV_COPROC_SUPPORTED
bool
default y
Expand Down
1 change: 1 addition & 0 deletions components/soc/esp32s2/include/soc/soc_caps.h
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,7 @@
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_ULP_FSM_SUPPORTED 1
#define SOC_RISCV_COPROC_SUPPORTED 1
#define SOC_USB_OTG_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
Expand Down
4 changes: 4 additions & 0 deletions components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,10 @@ config SOC_ULP_SUPPORTED
bool
default y

config SOC_ULP_FSM_SUPPORTED
bool
default y

config SOC_RISCV_COPROC_SUPPORTED
bool
default y
Expand Down
1 change: 1 addition & 0 deletions components/soc/esp32s3/include/soc/soc_caps.h
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_CACHE_SUPPORT_WRAP 1
#define SOC_ULP_SUPPORTED 1
#define SOC_ULP_FSM_SUPPORTED 1
#define SOC_RISCV_COPROC_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_USB_OTG_SUPPORTED 1
Expand Down
3 changes: 3 additions & 0 deletions components/ulp/.build-test-rules.yml
Original file line number Diff line number Diff line change
@@ -1,5 +1,8 @@
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps

components/ulp/test_apps/lp_core:
disable:
- if: SOC_LP_CORE_SUPPORTED != 1
components/ulp/test_apps/ulp_fsm:
enable:
- if: SOC_ULP_SUPPORTED == 1
Expand Down
12 changes: 12 additions & 0 deletions components/ulp/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,18 @@ if(CONFIG_SOC_ULP_SUPPORTED OR CONFIG_SOC_RISCV_COPROC_SUPPORTED)
endif()
endif()

if(CONFIG_ULP_COPROC_TYPE_LP_CORE)
list(APPEND includes
ulp_common/include
ulp_common/include/${target})

list(APPEND srcs
"lp_core/lp_core.c")

list(APPEND includes
"lp_core/include")
endif()

idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES driver esp_adc)
Expand Down
15 changes: 9 additions & 6 deletions components/ulp/Kconfig
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
menu "Ultra Low Power (ULP) Co-processor"
depends on (SOC_ULP_SUPPORTED || SOC_RISCV_COPROC_SUPPORTED)
depends on (SOC_ULP_SUPPORTED || SOC_RISCV_COPROC_SUPPORTED || SOC_LP_CORE_SUPPORTED)

config ULP_COPROC_ENABLED
bool "Enable Ultra Low Power (ULP) Co-processor"
Expand All @@ -11,26 +11,29 @@ menu "Ultra Low Power (ULP) Co-processor"
choice ULP_COPROC_TYPE
prompt "ULP Co-processor type"
depends on ULP_COPROC_ENABLED
default ULP_COPROC_TYPE_FSM if IDF_TARGET_ESP32
default ULP_COPROC_TYPE_RISCV if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
help
Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
Please note that ESP32 only supports ULP FSM.

config ULP_COPROC_TYPE_FSM
bool "ULP FSM (Finite State Machine)"
depends on SOC_ULP_FSM_SUPPORTED
config ULP_COPROC_TYPE_RISCV
bool "ULP RISC-V"
depends on !IDF_TARGET_ESP32
depends on SOC_RISCV_COPROC_SUPPORTED
config ULP_COPROC_TYPE_LP_CORE
bool "LP core RISC-V"
depends on SOC_LP_CORE_SUPPORTED
endchoice

config ULP_COPROC_RESERVE_MEM
int
prompt "RTC slow memory reserved for coprocessor"
depends on ULP_COPROC_ENABLED
default 512 if IDF_TARGET_ESP32
default 4096 if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
range 32 8176
default 4096 if !IDF_TARGET_ESP32
range 32 8176 if !IDF_TARGET_ESP32C6
range 32 16352 if IDF_TARGET_ESP32C6
help
Bytes of memory to reserve for ULP Co-processor firmware & data.
Data is reserved at the beginning of RTC slow memory.
Expand Down
27 changes: 22 additions & 5 deletions components/ulp/cmake/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,12 @@ add_executable(${ULP_APP_NAME})
set(CMAKE_EXECUTABLE_SUFFIX ".elf")

option(ULP_COCPU_IS_RISCV "Use RISC-V based ULP" OFF)
option(ULP_COCPU_IS_LP_CORE "Use RISC-V based LP Core" OFF)

message(STATUS "Building ULP app ${ULP_APP_NAME}")

# Check the supported assembler version
if(NOT ULP_COCPU_IS_RISCV)
if(NOT (ULP_COCPU_IS_RISCV OR ULP_COCPU_IS_LP_CORE))
check_expected_tool_version("esp32ulp-elf" ${CMAKE_ASM_COMPILER})
endif()

Expand All @@ -33,9 +34,12 @@ list(APPEND ULP_PREPROCESSOR_ARGS -D__ASSEMBLER__)
# Pre-process the linker script
if(ULP_COCPU_IS_RISCV)
set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/ulp_riscv.ld)
elseif(ULP_COCPU_IS_LP_CORE)
set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/lp_core_riscv.ld)
else()
set(ULP_LD_TEMPLATE ${IDF_PATH}/components/ulp/ld/ulp_fsm.ld)
endif()

get_filename_component(ULP_LD_SCRIPT ${ULP_LD_TEMPLATE} NAME)
add_custom_command(OUTPUT ${ULP_LD_SCRIPT}
COMMAND ${CMAKE_C_COMPILER} -E -P -xc -o ${ULP_LD_SCRIPT} ${ULP_PREPROCESSOR_ARGS} ${ULP_LD_TEMPLATE}
Expand Down Expand Up @@ -72,8 +76,19 @@ if(ULP_COCPU_IS_RISCV)
target_link_options(${ULP_APP_NAME} PRIVATE "-Wl,--no-warn-rwx-segments")
target_compile_definitions(${ULP_APP_NAME} PRIVATE IS_ULP_COCPU)

else()
elseif(ULP_COCPU_IS_LP_CORE)
list(APPEND ULP_S_SOURCES
"${IDF_PATH}/components/ulp/lp_core/lp_core/start.S"
"${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_startup.c")

target_link_options(${ULP_APP_NAME} PRIVATE "-nostartfiles")
target_link_options(${ULP_APP_NAME} PRIVATE "-Wl,--no-warn-rwx-segments")
target_link_options(${ULP_APP_NAME} PRIVATE -Wl,--gc-sections)
target_link_options(${ULP_APP_NAME} PRIVATE -Wl,-Map=${CMAKE_CURRENT_BINARY_DIR}/${ULP_APP_NAME}.map)
target_sources(${ULP_APP_NAME} PRIVATE ${ULP_S_SOURCES})
target_include_directories(${ULP_APP_NAME} PRIVATE "${IDF_PATH}/components/ulp/lp_core/lp_core/include")

else()
foreach(ulp_s_source ${ULP_S_SOURCES})
get_filename_component(ulp_ps_source ${ulp_s_source} NAME_WE)
set(ulp_ps_output ${CMAKE_CURRENT_BINARY_DIR}/${ulp_ps_source}.ulp.S)
Expand All @@ -96,9 +111,11 @@ else()

endif()

# Currently all the supported targets have the same base address of the ULP memory in the CPU address space.
# Modify this or pull this out of some SoC header file, if that becomes necessary.
set(ULP_BASE_ADDR "0x50000000")
if(ULP_COCPU_IS_LP_CORE)
set(ULP_BASE_ADDR "0x0")
else()
set(ULP_BASE_ADDR "0x50000000")
endif()

# Dump the list of global symbols in a convenient format
add_custom_command(OUTPUT ${ULP_APP_NAME}.sym
Expand Down
15 changes: 15 additions & 0 deletions components/ulp/cmake/toolchain-lp-core-riscv.cmake
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
# CMake toolchain file for ULP LP core
set(CMAKE_SYSTEM_NAME Generic)

set(CMAKE_C_COMPILER "riscv32-esp-elf-gcc")
set(CMAKE_CXX_COMPILER "riscv32-esp-elf-g++")
set(CMAKE_ASM_COMPILER "riscv32-esp-elf-gcc")

set(CMAKE_C_FLAGS "-Os -march=rv32imac_zicsr_zifencei -mdiv -fdata-sections -ffunction-sections"
CACHE STRING "C Compiler Base Flags")
set(CMAKE_CXX_FLAGS "-Os -march=rv32imac_zicsr_zifencei -mdiv -fdata-sections -ffunction-sections"
CACHE STRING "C++ Compiler Base Flags")
set(CMAKE_ASM_FLAGS "-march=rv32imac -x assembler-with-cpp"
CACHE STRING "Assembler Base Flags")
set(CMAKE_EXE_LINKER_FLAGS "-march=rv32imac_zicsr_zifencei --specs=nano.specs --specs=nosys.specs"
CACHE STRING "Linker Base Flags")
4 changes: 0 additions & 4 deletions components/ulp/component_ulp_common.cmake
Original file line number Diff line number Diff line change
@@ -1,7 +1,3 @@
message(WARNING "Embedding ULP binary by including \
${IDF_PATH}/components/ulp/component_ulp_common.cmake is deprecated. Use `ulp_embed_binary` instead. \
See API Guide for more details.")

spaces2list(ULP_S_SOURCES)
spaces2list(ULP_EXP_DEP_SRCS)

Expand Down
59 changes: 59 additions & 0 deletions components/ulp/ld/lp_core_riscv.ld
Original file line number Diff line number Diff line change
@@ -0,0 +1,59 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"

ENTRY(reset_vector)

MEMORY
{
/*first 128byte for exception/interrupt vectors*/
vector_table(RX) : ORIGIN = 0x50000000, LENGTH = 0x80
ram(RWX) : ORIGIN = 0x50000080, LENGTH = CONFIG_ULP_COPROC_RESERVE_MEM - 0x80
}

SECTIONS
{
.vector.text :
{
/*exception/interrupt vectors*/
__mtvec_base = .;
KEEP (*(.init.vector .init.vector.*))
} > vector_table

. = ORIGIN(ram);

.text ALIGN(4):
{
*(.text.vectors) /* Default reset vector must link to offset 0x80 */
*(.text)
*(.text*)
} >ram

.rodata ALIGN(4):
{
*(.rodata)
*(.rodata*)
} > ram

.data ALIGN(4):
{
*(.data)
*(.data*)
*(.sdata)
*(.sdata*)
} > ram

.bss ALIGN(4) :
{
*(.bss)
*(.bss*)
*(.sbss)
*(.sbss*)
PROVIDE(end = .);
} >ram

__stack_top = ORIGIN(ram) + LENGTH(ram);
}
53 changes: 53 additions & 0 deletions components/ulp/lp_core/include/ulp_lp_core.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,53 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

#pragma once
#include <stdint.h>
#include <stddef.h>
#include <stdlib.h>
#include "esp_err.h"
#include "ulp_common.h"

#ifdef __cplusplus
extern "C" {
#endif


typedef enum {
ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU, // LP core is started by HP core (1 single wakeup)
} ulp_lp_core_wakeup_source_t;

/**
* @brief ULP LP core init parameters
*
*/
typedef struct {
ulp_lp_core_wakeup_source_t wakeup_source;
} ulp_lp_core_cfg_t;

/**
* @brief Configure the ULP
* and run the program loaded into RTC memory
*
* @return ESP_OK on success
*/
esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg);

/**
* @brief Load the program binary into RTC memory
*
* @param program_binary pointer to program binary
* @param program_size_bytes size of the program binary
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_SIZE if program_size_bytes is more than KiB
*/
esp_err_t ulp_lp_core_load_binary(const uint8_t* program_binary, size_t program_size_bytes);


#ifdef __cplusplus
}
#endif

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