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CD and WP in sdspi_slot_config_t used in sdspi_host_init_slot(...) are truncated during a bit shift inside the driver.
Even though pull-up resistors can't be enabled on some pins, their use shouldn't be prohibited. At worst a warning should be displayed. Maybe a note in the SDSPI docs would be worthwhile.
Expected Behavior
Set CD to GPIO_NUM_38 and WP to GPIO_NUM_37 should set CD to GPIO 38 and WP to GPIO 37.
Actual Behavior
Set CD to GPIO_NUM_38 and WP to GPIO_NUM_37 results in GPIO 6 and 5 getting the configuration. Numbers less than 32 work as expected.
As an exciting byproduct, GPIO 6 is used for flash, leading to an immediate core panic.
Notice cd=38 in the first line and GPIO[6] referenced on the second-to-last line.
D (886) sdspi_host: sdspi_host_init_slot: SPI3 miso=19 mosi=23 sck=18 cs=17 cd=38 wp=-1, dma_ch=1
D (895) spi: SPI3 use iomux pins.
D (898) intr_alloc: Connected src 31 to int 17 (cpu 0)
D (903) spi_hal: eff: 400, limit: 80000k(/0), 0 dummy, -1 delay
D (909) spi_master: SPI3: New device added to CS0, effective clock: 400kHz
I (916) gpio: GPIO[17]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (926) gpio: GPIO[6]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
Guru Meditation Error: Core 0 panic'ed (IllegalInstruction) at pc=400ee149. Setting bp and returning..
After patching bit shifts from (1 << ...) to (1LL << ...) on lines 336 and 343 of components/driver/sdspi_host.c.
D (886) sdspi_host: sdspi_host_init_slot: SPI3 miso=19 mosi=23 sck=18 cs=17 cd=38 wp=-1, dma_ch=1
D (895) spi: SPI3 use iomux pins.
D (898) intr_alloc: Connected src 31 to int 17 (cpu 0)
D (903) spi_hal: eff: 400, limit: 80000k(/0), 0 dummy, -1 delay
D (909) spi_master: SPI3: New device added to CS0, effective clock: 400kHz
I (916) gpio: GPIO[17]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (926) gpio: GPIO[38]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
The text was updated successfully, but these errors were encountered:
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changed the title
sdspi_host_init_slot truncates CD and WP GPIO numbers larger than 32
sdspi_host_init_slot truncates CD and WP GPIO numbers larger than 32 (IDFGH-2196)
Nov 15, 2019
* If WebServer.handleClient is run in a tight loop, it will starve other processes. So, if there is no connection, throw in a delay(1). Fixesespressif#4348
* Made a variable to control the delay behavior
Environment
Problem Description
CD and WP in
sdspi_slot_config_t
used insdspi_host_init_slot(...)
are truncated during a bit shift inside the driver.Even though pull-up resistors can't be enabled on some pins, their use shouldn't be prohibited. At worst a warning should be displayed. Maybe a note in the SDSPI docs would be worthwhile.
Expected Behavior
Set CD to GPIO_NUM_38 and WP to GPIO_NUM_37 should set CD to GPIO 38 and WP to GPIO 37.
Actual Behavior
Set CD to GPIO_NUM_38 and WP to GPIO_NUM_37 results in GPIO 6 and 5 getting the configuration. Numbers less than 32 work as expected.
As an exciting byproduct, GPIO 6 is used for flash, leading to an immediate core panic.
Code
Debug Logs
Notice
cd=38
in the first line andGPIO[6]
referenced on the second-to-last line.After patching bit shifts from
(1 << ...)
to(1LL << ...)
on lines 336 and 343 ofcomponents/driver/sdspi_host.c
.The text was updated successfully, but these errors were encountered: