examples/ethernet/enc28j60/ - CS hold time (IDFGH-5412)

[MTsimon]

Environment

• Development Kit: ESP32-S2-DevKitM-1
• Kit version : v1.0
• Module or chip used: ESP32-S2-MINI-1
• IDF version (run git describe --tags to find it): v4.3
• Build System: idf.py
• Compiler version: xtensa-esp32s2-elf-gcc (crosstool-NG esp-2020r3) 8.4.0
• Operating System: Windows
• (Windows only) environment type: Plain Command Prompt
• Using an IDE?: VScode
• Power Supply: USB

Problem Description

Chip select hold time is not correctly setup according to datasheet. MII and MAC registers requires at least 210 ns of CS hold time.

Expected Behavior

To be able to read and write PHY and MAC registers.

Actual Behavior

Reading a PHY register through MII gives incorrect result.

Code to reproduce this issue

    /* ENC28J60 ethernet driver is based on spi driver */
    spi_device_interface_config_t devcfg = {
        .command_bits = 3,
        .address_bits = 5,
        .mode = 0,
        .clock_speed_hz = CONFIG_EXAMPLE_ENC28J60_SPI_CLOCK_MHZ * 1000 * 1000,
        .spics_io_num = CONFIG_EXAMPLE_ENC28J60_CS_GPIO,
        .queue_size = 20
    };

Code to resolve this issue

    /* ENC28J60 ethernet driver is based on spi driver */
    spi_device_interface_config_t devcfg = {
        .command_bits = 3,
        .address_bits = 5,
        .mode = 0,
        .cs_ena_posttrans = 5,
        .clock_speed_hz = CONFIG_EXAMPLE_ENC28J60_SPI_CLOCK_MHZ * 1000 * 1000,
        .spics_io_num = CONFIG_EXAMPLE_ENC28J60_CS_GPIO,
        .queue_size = 20
    };

[kostaond]

Great job! Thank you for sending this fix! We've already been reported with issues related to reading the PHY registers but you've found the root cause and provided the fix. Highly appreciated. The issue will be fixed soon in the IDF.