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fix(esp32-c5): Use a longer reset delay with usb-serial/jtag to stabi…
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…lize boot-up
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mythbuster5 authored and radimkarnis committed Jun 17, 2024
1 parent d49837e commit 1059ec7
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Showing 2 changed files with 10 additions and 3 deletions.
6 changes: 3 additions & 3 deletions esptool/reset.py
Original file line number Diff line number Diff line change
Expand Up @@ -148,13 +148,13 @@ class HardReset(ResetStrategy):
Can be used to reset out of the bootloader or to restart a running app.
"""

def __init__(self, port, uses_usb_otg=False):
def __init__(self, port, uses_usb=False):
super().__init__(port)
self.uses_usb_otg = uses_usb_otg
self.uses_usb = uses_usb

def reset(self):
self._setRTS(True) # EN->LOW
if self.uses_usb_otg:
if self.uses_usb:
# Give the chip some time to come out of reset,
# to be able to handle further DTR/RTS transitions
time.sleep(0.2)
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7 changes: 7 additions & 0 deletions esptool/targets/esp32c5.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@

from .esp32c6 import ESP32C6ROM
from ..loader import ESPLoader
from ..reset import HardReset


class ESP32C5ROM(ESP32C6ROM):
Expand All @@ -24,6 +25,8 @@ class ESP32C5ROM(ESP32C6ROM):
PCR_SYSCLK_XTAL_FREQ_V = 0x7F << 24
PCR_SYSCLK_XTAL_FREQ_S = 24

UARTDEV_BUF_NO = 0x4085F51C # Variable in ROM .bss which indicates the port in use

# Magic value for ESP32C5
CHIP_DETECT_MAGIC_VALUE = [0x8082C5DC]

Expand Down Expand Up @@ -67,6 +70,10 @@ def get_crystal_freq_rom_expect(self):
self.read_reg(self.PCR_SYSCLK_CONF_REG) & self.PCR_SYSCLK_XTAL_FREQ_V
) >> self.PCR_SYSCLK_XTAL_FREQ_S

def hard_reset(self):
print("Hard resetting via RTS pin...")
HardReset(self._port, self.uses_usb_jtag_serial())()

def change_baud(self, baud):
if not self.IS_STUB:
crystal_freq_rom_expect = self.get_crystal_freq_rom_expect()
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