a reload method makes it easier to keep allocated stuff

make reenables optional

Conflicts:
	src/apps/intel/intel10g.lua

src/apps/intel/intel10g.lua

@@ -556,6 +556,41 @@ function M_vf:close()
    return M_sf.close(self)
 end
 
+function M_vf:reconfig(opts)
+--    self:disable_transmit()
+--       :disable_receive()
+
+   local poolnum = self.poolnum or 0
+   local pf = self.pf
+
+   do
+      pf.r.PFVFSPOOF[math.floor(poolnum/8)]:clr(bits{MACAS=poolnum%8, VLANAS=poolnum%8+8})
+      pf.r.PFVMVIR[poolnum](0x00)
+      local msk = bits{PoolEna=poolnum%32}
+      for vlan_index = 0, 63 do
+         pf.r.PFVLVFB[2*vlan_index + math.floor(poolnum/32)]:clr(msk)
+      end
+   end
+   -- TODO: unset mirror
+   -- unset MAC
+   do
+      local msk = bits{Ena=self.poolnum%32}
+      for mac_index = 0, 127 do
+         pf.r.MPSAR[2*mac_index + math.floor(poolnum/32)]:set(msk)
+      end
+   end
+
+   return self
+      :set_MAC(opts.macaddr)
+      :set_mirror(opts.mirror)
+      :set_VLAN(opts.vlan)
+      :set_rx_stats(opts.rxcounter)
+      :set_tx_stats(opts.txcounter)
+      :set_tx_rate(opts.rate_limit, opts.priority)
+      :enable_receive()
+      :enable_transmit()
+end
+
 function M_vf:init (opts)
    return self
       :init_dma_memory()
@@ -602,15 +637,17 @@ function M_vf:enable_receive()
    return self
 end
 
-function M_vf:disable_receive()
+function M_vf:disable_receive(reenable)
    self.r.RXDCTL:clr(bits{Enable=25})
    self.r.RXDCTL:wait(bits{Enable=25}, 0)
    C.usleep(100)
    -- TODO free packet buffers
    self.pf.r.PFVFRE[math.floor(self.poolnum/32)]:clr(bits{VFRE=self.poolnum%32})
 
-   self.r.RXDCTL(bits{Enable=25, VME=30})
---    self.r.RXDCTL:wait(bits{enable=25})
+   if reenable then
+      self.r.RXDCTL(bits{Enable=25, VME=30})
+   --    self.r.RXDCTL:wait(bits{enable=25})
+   end
    return self
 end
 
@@ -633,16 +670,18 @@ function M_vf:enable_transmit()
    return self
 end
 
-function M_vf:disable_transmit()
+function M_vf:disable_transmit(reenable)
    -- TODO: wait TDH==TDT
    -- TODO: wait all is written back: DD bit or Head_WB
    self.r.TXDCTL:clr(bits{Enable=25})
    self.r.TXDCTL:set(bits{SWFLSH=26})
    self.r.TXDCTL:wait(bits{Enable=25}, 0)
    self.pf.r.PFVFTE[math.floor(self.poolnum/32)]:clr(bits{VFTE=self.poolnum%32})
 
-   self.r.TXDCTL:set(bits{Enable=25, SWFLSH=26})
---    self.r.TXDCTL:wait(bits{Enable=25})
+   if reenable then
+      self.r.TXDCTL:set(bits{Enable=25, SWFLSH=26})
+   --    self.r.TXDCTL:wait(bits{Enable=25})
+   end
    return self
 end
 

src/apps/intel/intel_app.lua

@@ -66,6 +66,14 @@ function Intel82599:stop()
    end
 end
 
+
+function Intel82599:reconfig(arg)
+   local conf = config.parse_app_arg(arg)
+   assert((not not self.dev.pf) == (not not conf.vmdq), "Can't reconfig from VMDQ to single-port or viceversa")
+
+   self.dev:reconfig(conf)
+end
+
 -- Allocate receive buffers from the given freelist.
 function Intel82599:set_rx_buffer_freelist (fl)
    self.rx_buffer_freelist = fl