Patch Status 27156-RISCV_Various_ifconversion_fixes_and_improvements-14

[github-actions]

Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/6918705754

Patch information

Applied patches: 1 -> 14
Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=27156
Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/alpine.DEB.2.20.2311180416250.5892@tpp.orcam.me.uk/
Patch id: 80255

Build Targets

Some targets are built as multilibs. If a build target ends with multilib, please refer to the table below to see all the targets within that multilib.

Target name	-march string
newlib-rv64gc-lp64d-multilib	rv32gc-ilp32d, rv64gc-lp64d
newlib-rv64gcv-lp64d-multilib	rv64gcv-lp64d
linux-rv64gcv-lp64d-multilib	rv32gcv-ilp32d, rv64gcv-lp64d

Target Information

Target Shorthand	-march string
Bitmanip	gc_zba_zbb_zbc_zbs

Notes

Testsuite checks are in beta testing stages. Results are unstable and may be inaccurate.

[github-actions]

Lint Status

Lint passed

[github-actions]

Apply Status

Target	Status
Baseline hash: gcc-mirror/gcc@20a3c74	Failed
Tip of tree hash: gcc-mirror/gcc@af7fa31	Failed

Command

> git am ../patches/*.patch --whitespace=fix -q --3way --empty=drop

Output

error: sha1 information is lacking or useless (gcc/config/riscv/riscv.cc).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0004 RISC-V: Also invert the cond-move condition for GEU and LEU
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---
 gcc/config/riscv/riscv.cc |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

gcc-riscv-expand-conditional-move-geu-leu.diff

Index: gcc/gcc/config/riscv/riscv.cc
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.cc
+++ gcc/gcc/config/riscv/riscv.cc
@@ -4142,7 +4142,7 @@ riscv_expand_conditional_move (rtx dest,
 	  /* If riscv_expand_int_scc inverts the condition, then it will
 	     flip the value of INVERT.  We need to know where so that
 	     we can adjust it for our needs.  */
-	  if (code == LE || code == GE)
+	  if (code == LE || code == LEU || code == GE || code == GEU)
 	    invert_ptr = &invert;
 
 	  /* Emit an scc like instruction into a temporary

Additional information