equivalent tiles: added SLICEL equivalent tile

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
f4pga · May 6, 2019 · be517ea · be517ea
1 parent 3f1744f
commit be517ea
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Showing 2 changed files with 2 additions and 6 deletions.
diff --git a/xc7/archs/artix7/tiles/slicel/CMakeLists.txt b/xc7/archs/artix7/tiles/slicel/CMakeLists.txt
@@ -3,4 +3,5 @@ project_xray_tile(
   TILE SLICEL
   SITE_AS_TILE
   SITE_TYPES SLICEL/SLICEL0
+  EQUIVALENT_TILES SLICEM
   )
diff --git a/xc7/utils/prjxray_physical_tile_import.py b/xc7/utils/prjxray_physical_tile_import.py
@@ -29,18 +29,13 @@
 PORT_TAGS = ['input', 'output', 'clock']
 
 
-# FIXME: For now the prefix is not used as PR https://github.com/SymbiFlow/symbiflow-arch-defs/pull/665
-#        is not yet merged.
 def prefix_name(tile, active=False):
     """ Add tile prefix.
 
     This avoids namespace collision when embedding a site (e.g. SLICEL) as a
     tile.
     """
-    if active:
-        return 'BLK-TL-' + tile
-
-    return tile
+    return 'BLK-TL-' + tile
 
 
 def object_ref(pb_name, pin_name, pin_idx=None):