Support for IDDR and ODDR #1502

mkurc-ant · 2020-05-25T14:58:45Z

This PR adds support for IDDR and ODDR primitives.

The IDDR is added as another mode of the ILOGICE3 pb_type. The connection IDELAY->IDDR is modeled as a mux - no need for separate pb_types.

An ODDR can be used to drive either O or T of an (I)OBUFT(DS). Two independent ODDRs can be packed into the same OLOGIC site to drive O and T independently.

For that the OLOGICE3 pb_type has two modes: OSERDESE2 and OLOGIC. In the second mode there are two almost identical child pb_types - one for ODDR for OQ and one for ODDR for TQ. These pb_types can operate independently either in the ODDR mode or a pass-through mode. This allows to have all combinations of ODDR uses.

Depending on where an ODDR is used, different fasm features have to be emitted. Fortunately for O and T they have one-to-one correspondences. The same blif models for both could be used. They are however nested i different pb_types that provide necessary parameters to fasm features mappings.

For the updated OLOGICE3 model to work the T connection for OBUF had to be made explicit. The IOB architecture has been modified to have the OBUFT by default. That allowed 'O' and 'T' paths to be split and made fully independent.

The issue with Vivado routing OBUFT.T to const1 + enabling inversion while it is logically connected to const0 has been fixed according to the suggestion in the issue: #1514

mkurc-ant · 2020-07-08T08:21:00Z

I didn't see any CI errors besides #1400 so I rebased it on top of master. Now the CI should pass.

litghost · 2020-07-08T14:04:36Z

xc/xc7/fasm2bels/iob_models.py

+    - Detects whether there is an OBUFT with T input routed to const1. If so
+      then checks whether the ZINV_T1 inverter is enabled in the neighboring
+      OLOGIC site. If both cases are true then the OBUFT is replaced with an
+      OBUF.


Good comment, thanks!

litghost · 2020-07-08T14:05:32Z

xc/xc7/fasm2bels/iob_models.py

+        return
+
+    # Get the neighboring IOI3 tile prefix and loc
+    ioi_tile_loc = site.tile.rsplit("_", maxsplit=1)[1]


Rather than doing a string replace here, why not walk 1 tile to the left or right? That would be more robust?

xc/xc7/fasm2bels/ioi_models.py

litghost · 2020-07-08T14:08:52Z

xc/xc7/fasm2bels/ioi_models.py

+        data_rate = '"DDR"'
+    bel.parameters['DATA_RATE'] = data_rate
+
+    # TODO: There shouldn't be mixed width in FASM features.


This feels like it could crop up in a new fasm2bels failure in the future. Is it possible to add a failing test now to demostrate the issue you are mentioning here?

@litghost You mean add it and then disable? (we want green CI). I can think of a test with data width of eg. 4 that cannot be decoded now.

@litghost You mean add it and then disable? (we want green CI). I can think of a test with data width of eg. 4 that cannot be decoded now.

That is one way to go. I think the valid options are:

Create and issue, and attach a failing test case so that it can be fixed in the future

Create the failing test case and fix it in this PR

The TODO by itself is insufficient.

I'll go with an issue then. Solving it probably requires adjustment to prjxray fuzzers, and I think that this PR is already kind of big.

There: #1589

xc/xc7/techmap/cells_map.v

litghost · 2020-07-08T20:55:57Z

This PR needs to be rebased.

mkurc-ant · 2020-07-10T13:42:34Z

@litghost I've discovered an issue with handling of IDDR vs. IDDR_2CLK.

In the techmap I map IDDR to the two clock version by connecting both C and CB to the same signal and setting the IS_CB_INVERTER parameter. Since there are no bits for that I wonder how should I handle this. For an IDDR Vivado always show that both CLK and CLKB of the site are connected to the same net and that the CLKB inverter is enabled.

Similarly, there is an issue in fasm2bels - whenever I decode a IDDR_2CLK with C and CB connected to the same net, Vivado complains that this is illegal.

@acomodi You have dealt with ISERDES stuff which appears to be similar. Have you encountered issues with CLKB inversion ?

acomodi · 2020-07-10T13:49:46Z

@mkurc-ant , as far as I understood with the ISERDES, the CLKB inverter is not enabled by any feature, with, or without it, the bitstream remains the same. What I have done in fasm2bels, at the time, was to add the IS_CLKB_INVERTED parameter to the ISERDES, but still assign the same net to CLK and CLKB. This avoids Vivado complaining about the clock signals being the same.

mkurc-ant · 2020-07-10T13:51:52Z

@acomodi Thanks, I'll try that.

mkurc-ant · 2020-07-10T14:26:57Z

@acomodi That did the trick! I now have IDDR and ODDR working in hardware as well as correct decoding in fasm2bels.

Although there is a fasm difference:

 HCLK_CMT_X8Y26.HCLK_CMT_CK_BUFHCLK9_USED

 HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_ACTIVE
-HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_USED
 HCLK_CMT_L_X106Y26.HCLK_CMT_CK_BUFHCLK6_USED
 HCLK_CMT_L_X106Y26.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL0

But I probably know the cause, we shouldn't emit CCIOn_USED feature for routes through HCLK_CMT_MUX_OUT_FREQ_REFn.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…ey have OSERDES connected. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

This reverts commit 1a50773. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…SERDES Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

probot-autolabeler bot added lang-python Issue uses (or requires) Python language. lang-verilog Issue uses (or requires) Verilog language. lang-xml Issues uses (or requires) XML language. type-utils Issues is related to the scripts inside the repo. type-vpr labels May 25, 2020

mkurc-ant force-pushed the iddr_oddr branch 5 times, most recently from c113787 to 77eb3f4 Compare July 7, 2020 07:30

mkurc-ant changed the title ~~[WIP] Support for IDDR and ODDR~~ Support for IDDR and ODDR Jul 7, 2020

mkurc-ant linked an issue Jul 7, 2020 that may be closed by this pull request

Add support for IDDR primitives #1432

Closed

mkurc-ant mentioned this pull request Jul 7, 2020

Cannot pack OSERDES + OBUFDS together #1469

Closed

mkurc-ant force-pushed the iddr_oddr branch from ea2534b to 36b5a7c Compare July 8, 2020 08:19

mkurc-ant requested review from litghost and acomodi July 8, 2020 08:21

litghost reviewed Jul 8, 2020

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mkurc-ant force-pushed the iddr_oddr branch from 36b5a7c to 131c8ef Compare July 10, 2020 13:36

probot-autolabeler bot added the type-docs Issue is related to documentation. label Jul 10, 2020

mkurc-ant and others added 25 commits August 13, 2020 11:18

Complete support for IDDR

5b17b61

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Complete support for ODDR (for OQ)

8ca34a0

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added techmap for OBUFT

80a7ce8

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Updated arch+techmap, added a test for ODDR driving T

e90217c

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Code formatting

97304f4

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added timing data for IDDR and ODDR

f36b49c

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added test for OBUF, OBUFT, OBUFDS and OBUFTDS

111a220

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Fix after rebase

9bff776

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added explicit inverter for OBUFT.T that can fit into OLOGIC site

3e7f693

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added the (* iopad_external_pin *) attribute to iobs.v

36e0fa8

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Cleaned up add_pack_patterns.py

39e135e

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Cleaned up add_pack_patterns.py

f4f756c

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added OSERDES version with TQ bypassed

f62319e

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Changed yosys/synth.tcl so that OBUFDS and OBUFTDS can "know" that th…

b3b900b

…ey have OSERDES connected. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Code formatting

36973f1

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Changed pinout for IDDR/ODDR placement tests

0a91bc9

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added a working hardware test for IDDR/ODDR

07ea1f6

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added README.md to the IDDR/ODDR test.

f098246

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Corrected emission of CCIOn_ACTIVE fasm features

ae6fef0

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Revert "Added OSERDES version with TQ bypassed"

bb0cd99

This reverts commit 1a50773. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added a routing mux to bypass OSERDES when OBUFT.T is routed to 0

525583d

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Removed a verilog hack, fixed techmap failure reporting for ISERDES/O…

2d720e9

…SERDES Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added dummy timing to the T_INV pb_type

e68a538

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added comments

ceea71c

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

iddr: remove Z_MEMORY from the fasm features

6de04b5

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

acomodi force-pushed the iddr_oddr branch from 5ee84aa to 6de04b5 Compare August 13, 2020 09:19

acomodi added the kokoro:force-run label Aug 17, 2020

symbiflow-kokoro removed the kokoro:force-run label Aug 17, 2020

acomodi merged commit d379f07 into f4pga:master Aug 18, 2020

umarcor deleted the iddr_oddr branch March 22, 2022 21:50

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Support for IDDR and ODDR #1502

Support for IDDR and ODDR #1502

mkurc-ant commented May 25, 2020 •

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mkurc-ant commented Jul 8, 2020

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litghost commented Jul 8, 2020

mkurc-ant commented Jul 10, 2020 •

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mkurc-ant commented Jul 10, 2020

mkurc-ant commented Jul 10, 2020

Support for IDDR and ODDR #1502

Support for IDDR and ODDR #1502

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mkurc-ant commented May 25, 2020 • edited

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litghost commented Jul 8, 2020

mkurc-ant commented Jul 10, 2020 • edited

acomodi commented Jul 10, 2020 • edited

mkurc-ant commented Jul 10, 2020

mkurc-ant commented Jul 10, 2020

mkurc-ant commented May 25, 2020 •

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mkurc-ant commented Jul 10, 2020 •

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acomodi commented Jul 10, 2020 •

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