Fix clock placement in devices with limited grid

[rw1nkler]

This commit adds the ability to verify if the clock location is available in the FPGA grid before placement. It uses architecture XML for the verification.

Resolves #1517

[mithro]

PTAL - @tcal-x

[tcal-x]

PTAL - @tcal-x

I will try the script on the test where I had to add the workaround LOC constraints. I need to rebuild rr_graph in my sandbox though so it will be a few hours before I have an update.

[tcal-x]

This fix may be unrelated to the issue I'm seeing. In any case, I see exactly the same error using the new version of the script, just the line numbers are different. In my case, the script has difficulty placing the PLLE2_ADV if it is not constrained. I'm targeting the full 100T chip.

This is the error (line numbers are using the new version from this PR):

Traceback (most recent call last):
  File "/home/tcal/2nd-tcal-x/symbiflow-arch-defs/xc/common/utils/prjxray_create_place_constraints.py", line 734, in <module>
    main()
  File "/home/tcal/2nd-tcal-x/symbiflow-arch-defs/xc/common/utils/prjxray_create_place_constraints.py", line 722, in main
    vpr_grid, loc_in_use, block_locs, blocks, grid_capacities):
  File "/home/tcal/2nd-tcal-x/symbiflow-arch-defs/xc/common/utils/prjxray_create_place_constraints.py", line 519, in place_clocks
    for potential_loc in sorted(available_placements[key]):
KeyError: ('PLLE2_ADV', 5)

[rw1nkler]

I have changed the script to use limited device grid. Additionally, now it is possible to use only top/bottom half of the device.

The script does not check if the used resource is available in the given clock domain. (This bug was present before) Because of that, after limiting the device grid, sometimes it tries to place i.e. PLLE2_ADV instance in the clock domain that, does not have it. I fixed the problem by excluding almost empty clock domains from the basys-bottom device definition when the problem occurs.

A universal solution requires rearranging the constraint problem and adding proper checks of variable domains to clocking resources like i.e. PLLs.

[litghost]

Small change requested

[litghost]

LGTM, merge if green