Merge pull request YosysHQ#143 from cr1901/bels-rg

Reverse belsUphill and belsDownhill assignments- agreed to be typo.
f4pga · Jun 12, 2020 · 5c9f6ad · 5c9f6ad
2 parents a1b4327 + f5f7090
commit 5c9f6ad
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/libtrellis/src/RoutingGraph.cpp b/libtrellis/src/RoutingGraph.cpp
@@ -147,7 +147,7 @@ void RoutingGraph::add_bel_input(RoutingBel &bel, ident_t pin, int wire_x, int w
     belId.loc = bel.loc;
     add_wire(wireId);
     bel.pins[pin] = make_pair(wireId, PORT_IN);
-    tiles[wireId.loc].wires[wireId.id].belsUphill.push_back(make_pair(belId, pin));
+    tiles[wireId.loc].wires[wireId.id].belsDownhill.push_back(make_pair(belId, pin));
 }
 
 void RoutingGraph::add_bel_output(RoutingBel &bel, ident_t pin, int wire_x, int wire_y, ident_t wire_name) {
@@ -159,7 +159,7 @@ void RoutingGraph::add_bel_output(RoutingBel &bel, ident_t pin, int wire_x, int
     belId.loc = bel.loc;
     add_wire(wireId);
     bel.pins[pin] = make_pair(wireId, PORT_OUT);
-    tiles[wireId.loc].wires[wireId.id].belsDownhill.push_back(make_pair(belId, pin));
+    tiles[wireId.loc].wires[wireId.id].belsUphill.push_back(make_pair(belId, pin));
 }
 
 }