minitests: Add input DELAYF minitest

Signed-off-by: David Shah <dave@ds0.me>
f4pga · Nov 18, 2019 · 5d1cfae · 5d1cfae
1 parent dc10b8a
commit 5d1cfae
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/minitests/iologic/idelay.v b/minitests/iologic/idelay.v
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+module idelay(input D, MOVE, LOADN, DIR, output Q, CFLAG);
+wire dly_out;
+DELAYF dly_f (.A(D), .MOVE(MOVE), .LOADN(LOADN), .DIRECTION(DIR), .Z(dly_out), .CFLAG(CFLAG));
+assign Q = ~dly_out;
+endmodule
+