Merge pull request YosysHQ#113 from rrika/master

libtrellis: offer serialise_chip/serialise_chip_delta in Python api
f4pga · Jan 2, 2020 · d8c5e9d · d8c5e9d
2 parents 4e0b215 + 2238e31
commit d8c5e9d
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Showing 3 changed files with 22 additions and 1 deletion.
diff --git a/libtrellis/include/Bitstream.hpp b/libtrellis/include/Bitstream.hpp
@@ -52,6 +52,9 @@ class Bitstream {
     static Bitstream serialise_chip_partial(const Chip &chip, const vector<uint32_t> &frames, const map<string, string> options);
     static Bitstream generate_jump(uint32_t address);
 
+    static Bitstream serialise_chip_py(const Chip &chip);
+    static Bitstream serialise_chip_delta_py(const Chip &chip1, const Chip &chip2);
+
     // Deserialise a bitstream to a Chip
     Chip deserialise_chip();
     Chip deserialise_chip(boost::optional<uint32_t> idcode = boost::optional<uint32_t>());

diff --git a/libtrellis/src/Bitstream.cpp b/libtrellis/src/Bitstream.cpp
@@ -681,6 +681,10 @@ Bitstream Bitstream::generate_jump(uint32_t address) {
     return Bitstream(wr.get(), std::vector<string>());
 }
 
+Bitstream Bitstream::serialise_chip_py(const Chip &chip) {
+    return serialise_chip(chip, map<string, string>());
+}
+
 Bitstream Bitstream::serialise_chip(const Chip &chip, const map<string, string> options) {
     BitstreamReadWriter wr;
     // Preamble
@@ -825,6 +829,18 @@ Bitstream Bitstream::serialise_chip(const Chip &chip, const map<string, string>
     return Bitstream(wr.get(), chip.metadata);
 }
 
+Bitstream Bitstream::serialise_chip_delta_py(const Chip &chip1, const Chip &chip2)
+{
+    vector<uint32_t> frames;
+    for (int frame = 0; frame < chip2.cram.frames(); frame++) {
+        if (chip1.cram.data->at(frame) != chip2.cram.data->at(frame)) {
+            frames.push_back(frame);
+        }
+    }
+
+    return serialise_chip_partial(chip2, frames, map<string, string>());
+}
+
 Bitstream Bitstream::serialise_chip_partial(const Chip &chip, const vector<uint32_t> &frames, const map<string, string> options)
 {
     BitstreamReadWriter wr;

diff --git a/libtrellis/src/PyTrellis.cpp b/libtrellis/src/PyTrellis.cpp
@@ -58,8 +58,10 @@ BOOST_PYTHON_MODULE (pytrellis)
     class_<Bitstream>("Bitstream", no_init)
             .def("read_bit", &Bitstream::read_bit_py)
             .staticmethod("read_bit")
-            .def("serialise_chip", &Bitstream::serialise_chip)
+            .def("serialise_chip", &Bitstream::serialise_chip_py)
             .staticmethod("serialise_chip")
+            .def("serialise_chip_delta", &Bitstream::serialise_chip_delta_py)
+            .staticmethod("serialise_chip_delta")
             .def("write_bit", &Bitstream::write_bit_py)
             .def_readwrite("metadata", &Bitstream::metadata)
             .def_readwrite("data", &Bitstream::data)