Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Type check expressions #42

Open
fabianschuiki opened this issue Feb 3, 2018 · 1 comment
Open

Type check expressions #42

fabianschuiki opened this issue Feb 3, 2018 · 1 comment
Labels
L-vhdl Language: VHDL.

Comments

@fabianschuiki
Copy link
Owner

fabianschuiki commented Feb 3, 2018 •
edited
Loading

Perform a proper type check of expressions. This will require proper resolution of overloaded function calls and enum variants. Requires #40 and #41 to be done.
@fabianschuiki fabianschuiki added the L-vhdl Language: VHDL. label Feb 3, 2018
@fabianschuiki
Copy link
Owner Author

This is partially implemented. All primary expressions are properly type checked, except for function calls. Composite expressions (unary and binary operations, etc.) are not implemented yet.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
L-vhdl Language: VHDL.
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@fabianschuiki