Skip to content

fairchildfzc/32bit-Adder-Design

Repository files navigation

32bit-Adder-Design

People

  • Zichen Fan, EE, Tsinghua University
  • Songyao Tan, IME, Tsinghua University

Platform

  • Hspice

Structure

Results

Parameter Specification
Technology 180nm CMOS, Nominal Corner
Power Dissipation 324.8uW
Maximum Latency 1.843ns
Area 811.8um

About

Design a 32bit adder using HSpice

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages