Various fixes plus return port registering.

ferrandi · Jan 11, 2020 · 8a39727 · 8a39727
1 parent 3002254
commit 8a39727
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Showing 6 changed files with 24 additions and 13 deletions.
diff --git a/src/BambuParameter.cpp b/src/BambuParameter.cpp
@@ -831,7 +831,7 @@ void BambuParameter::PrintHelp(std::ostream& os) const
       << "    --registered-inputs=value\n"
       << "        Specify if inputs are registered or not:\n"
       << "             auto  - inputs are registered only for proxy functions (default)\n"
-      << "             top   - inputs are registered only for top and proxy functions\n"
+      << "             top   - inputs and return are registered only for top and proxy functions\n"
       << "             yes   - all inputs are registered\n"
       << "             no    - none of the inputs is registered\n\n"
       << "    --fsm-encoding=value\n"

diff --git a/src/HLS/scheduling/parametric_list_based.cpp b/src/HLS/scheduling/parametric_list_based.cpp
@@ -85,6 +85,7 @@
 #include "xml_document.hpp"
 
 #include "behavioral_helper.hpp"
+#include "call_graph_manager.hpp"  // for CallGraphManager, CallGrap...
 #include "string_manipulation.hpp" // for GET_CLASS
 
 #if !HAVE_UNORDERED
@@ -349,7 +350,7 @@ void parametric_list_based::CheckSchedulabilityConditions(const vertex& current_
                       ((!is_pipelined && n_cycles == 0 && current_starting_time > (current_cycle_starting_time)) && current_ending_time + setup_hold_time + phi_extra_time + scheduling_mux_margins > current_cycle_ending_time);
    if(cannotBeChained0)
       return;
-   chainingRetCond = (unbounded || cstep_has_RET_conflict /*|| current_starting_time > (current_cycle_starting_time)*/) && (GET_TYPE(flow_graph, current_vertex) & TYPE_RET);
+   chainingRetCond = (unbounded || (cstep_has_RET_conflict && current_starting_time > (current_cycle_starting_time))) && (GET_TYPE(flow_graph, current_vertex) & TYPE_RET);
    if(chainingRetCond)
       return;
    if(cannotBeChained1)
@@ -383,6 +384,9 @@ void parametric_list_based::exec(const OpVertexSet& operations, ControlStep curr
    THROW_ASSERT(operations.size(), "At least one vertex is expected");
    const FunctionBehaviorConstRef FB = HLSMgr->CGetFunctionBehavior(funId);
    const OpGraphConstRef op_graph = FB->CGetOpGraph(FunctionBehavior::CFG);
+   const auto top_function_ids = HLSMgr->CGetCallGraphManager()->GetRootFunctions();
+   const unsigned int return_type_index = FB->CGetBehavioralHelper()->GetFunctionReturnType(funId);
+   auto registering_output_p = top_function_ids.find(funId) != top_function_ids.end() && return_type_index && parameters->getOption<std::string>(OPT_registered_inputs) == "top";
 
    /// The scheduling
    const ScheduleRef schedule = HLS->Rsch;
@@ -529,8 +533,8 @@ void parametric_list_based::exec(const OpVertexSet& operations, ControlStep curr
 #endif
    unsigned int cstep_vuses_ARRAYs = 0;
    unsigned int cstep_vuses_others = 0;
-   bool cstep_has_RET_conflict = false;
-   bool seen_cstep_has_RET_conflict = false;
+   bool cstep_has_RET_conflict = registering_output_p;
+   bool seen_cstep_has_RET_conflict = registering_output_p;
 
    OpVertexSet::const_iterator rv, rv_end = ready_vertices.end();
 
@@ -585,6 +589,7 @@ void parametric_list_based::exec(const OpVertexSet& operations, ControlStep curr
       bool unbounded = false;
       bool unbounded_RW = false;
       bool store_unbounded_check = false;
+      unsigned int n_scheduled_ops = 0;
       PRINT_DBG_MEX(DEBUG_LEVEL_VERY_PEDANTIC, debug_level, "      schedule->num_scheduled() " + std::to_string(schedule->num_scheduled()));
       PRINT_DBG_MEX(DEBUG_LEVEL_VERY_PEDANTIC, debug_level, "      already_sch " + std::to_string(already_sch));
       PRINT_DBG_MEX(DEBUG_LEVEL_VERY_PEDANTIC, debug_level, "      operations_number " + std::to_string(operations_number));
@@ -749,6 +754,16 @@ void parametric_list_based::exec(const OpVertexSet& operations, ControlStep curr
                   PRINT_DBG_MEX(DEBUG_LEVEL_VERY_PEDANTIC, debug_level, "            Scheduling of Control Vertex " + GET_NAME(flow_graph, current_vertex) + " postponed ");
                   continue;
                }
+
+               if((GET_TYPE(flow_graph, current_vertex) & TYPE_RET) && ((schedule->num_scheduled() - already_sch) == operations_number - 1) && n_scheduled_ops != 0 && registering_output_p)
+               {
+                  if(black_list.find(fu_type) == black_list.end())
+                     black_list.emplace(fu_type, OpVertexSet(flow_graph));
+                  black_list.at(fu_type).insert(current_vertex);
+
+                  PRINT_DBG_MEX(DEBUG_LEVEL_VERY_PEDANTIC, debug_level, "            Scheduling of Control Vertex " + GET_NAME(flow_graph, current_vertex) + " postponed to the next cycle to register the output");
+                  continue;
+               }
                if(!HLS->allocation_information->is_operation_bounded(flow_graph, current_vertex, fu_type) && RW_stmts.find(current_vertex) == RW_stmts.end() && (unbounded || unbounded_RW || is_live || store_unbounded_check))
                {
                   if(black_list.find(fu_type) == black_list.end())
@@ -1011,6 +1026,7 @@ void parametric_list_based::exec(const OpVertexSet& operations, ControlStep curr
                }
 
                /// scheduling is now possible
+               ++n_scheduled_ops;
                /// update resource usage
                used_resources[fu_type]++;
 
@@ -1198,7 +1214,7 @@ void parametric_list_based::exec(const OpVertexSet& operations, ControlStep curr
       /// clear the vises
       cstep_vuses_ARRAYs = cstep_vuses_ARRAYs > 0 ? cstep_vuses_ARRAYs - 1 : 0;
       cstep_vuses_others = cstep_vuses_others > 0 ? cstep_vuses_others - 1 : 0;
-      cstep_has_RET_conflict = false;
+      cstep_has_RET_conflict = registering_output_p;
       /// move to the next cycle
       ++current_cycle;
    }

diff --git a/src/wrapper/simulation/SimulationTool.cpp b/src/wrapper/simulation/SimulationTool.cpp
@@ -191,11 +191,6 @@ unsigned long long int SimulationTool::DetermineCycles(unsigned long long int& a
                THROW_ERROR("String not valid: " + line);
             }
             auto sim_cycles = boost::lexical_cast<unsigned long long int>(filevalues[1]);
-            /// Remove one cycle if primary input are registered
-            if(Param->getOption<std::string>(OPT_registered_inputs) == "top")
-            {
-               sim_cycles -= 1;
-            }
             if(filevalues.size() == 3)
             {
                if(filevalues[2] == "ns")

diff --git a/src/wrapper/synthesis/altera/AlteraBackendFlow.cpp b/src/wrapper/synthesis/altera/AlteraBackendFlow.cpp
@@ -285,7 +285,7 @@ void AlteraBackendFlow::create_sdc(const DesignParametersRef dp)
    if(!boost::lexical_cast<bool>(dp->parameter_values[PARAM_is_combinational]))
    {
       sdc_file << "create_clock -period " + dp->parameter_values[PARAM_clk_period] + " -name " + clock + " [get_ports " + clock + "]\n";
-      if(get_flow_name() != "Characterization" && boost::lexical_cast<bool>(dp->parameter_values[PARAM_connect_iob]))
+      if(get_flow_name() != "Characterization" && (boost::lexical_cast<bool>(dp->parameter_values[PARAM_connect_iob]) || (Param->IsParameter("profile-top") && Param->GetParameter<int>("profile-top") == 1)))
       {
          sdc_file << "set_min_delay 0 -from [all_inputs] -to [all_registers]\n";
          sdc_file << "set_min_delay 0 -from [all_registers] -to [all_outputs]\n";

diff --git a/src/wrapper/synthesis/lattice/LatticeBackendFlow.cpp b/src/wrapper/synthesis/lattice/LatticeBackendFlow.cpp
@@ -233,7 +233,7 @@ void LatticeBackendFlow::create_sdc(const DesignParametersRef dp)
    if(!boost::lexical_cast<bool>(dp->parameter_values[PARAM_is_combinational]))
    {
       sdc_file << "create_clock -period " + dp->parameter_values[PARAM_clk_period] + " -name " + clock + " [get_ports " + clock + "]\n";
-      if(boost::lexical_cast<bool>(dp->parameter_values[PARAM_connect_iob]))
+      if(boost::lexical_cast<bool>(dp->parameter_values[PARAM_connect_iob]) || (Param->IsParameter("profile-top") && Param->GetParameter<int>("profile-top") == 1))
          sdc_file << "set_max_delay " + dp->parameter_values[PARAM_clk_period] + " -from [all_inputs] -to [all_outputs]\n";
    }
    else

diff --git a/src/wrapper/synthesis/xilinx/vivado_flow_wrapper.cpp b/src/wrapper/synthesis/xilinx/vivado_flow_wrapper.cpp
@@ -80,7 +80,7 @@ void vivado_flow_wrapper::create_sdc(const DesignParametersRef& dp)
    if(!boost::lexical_cast<bool>(dp->parameter_values[PARAM_is_combinational]))
    {
       sdc_file << "create_clock -period " + dp->parameter_values[PARAM_clk_period] + " -name " + clock + " [get_ports " + clock + "]\n";
-      if(boost::lexical_cast<bool>(dp->parameter_values[PARAM_connect_iob]))
+      if(boost::lexical_cast<bool>(dp->parameter_values[PARAM_connect_iob]) || (Param->IsParameter("profile-top") && Param->GetParameter<int>("profile-top") == 1))
       {
          sdc_file << "set_max_delay " + dp->parameter_values[PARAM_clk_period] + " -from [all_inputs] -to [all_outputs]\n";
          sdc_file << "set_max_delay " + dp->parameter_values[PARAM_clk_period] + " -from [all_inputs] -to [all_registers]\n";