AVX2 implementation of DMVR SAD for VVC #214
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deblock, sao, alf skip, imtf, ipm, cqt_depth, cb_pos_x, cb_pos_y, cb_height, cp_mv, tb_pos_x0, tb_pos_y0, tb_width, tb_height
For luma, qp can only change at the CU level, so the qp tab size is related to the CU. For chroma, considering the joint CbCr, the QP tab size is related to the TU.
…threads memset tables in the main thread can become a bottleneck for the decoder. For example, if it takes 2% of the processing time for one core, the maximum achievable FPS will be 50. Move the memeset to worker threads will fix the issue.
Adds AVX2 assembly for SAD used in DMVR (decoder-side motion vector refinement). The main difference is that in VVC, SAD is only calculated on even rows of the PU to reduce complexity. Implements SAD via min/max/sub for 16bit values. DMVR is restricted to PUs whose width >= 8, height >=8 and width * height >= 128 (ie 8x8 is not a valid size).
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Messed up the rebase again |
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As per #212 (comment) this is based on ffmpeg/main and pulling into ffvvc/up
Adds AVX2 assembly for SAD used in DMVR (decoder-side motion vector refinement). The main difference is that in VVC, SAD is only calculated on even rows of the PU to reduce complexity. Implements SAD via min/max/sub for 16bit values.
DMVR is restricted to PUs whose width >= 8, height >=8 and width * height >= 128 (ie 8x8 is not a valid size).
Ran on AMD 7940HS