yariscv is an Yet Another RISC-V emulator
Implements rv32imac architecture with sv32 mmu... and it has a very dumb TLB cache implementation Implements clint, plic is a stub Implements litex-like UART(seems like it's working) Uses stdin and stdout as input for integrated UART
mkdir build && cd build
cmake ..
make
Run
./yariscv
Command line arguments
[-f|--firmare] - pass firmware to the emulator(opensbi is preferred)
[-i|--initrd] - pass linux initrd image
[-d|--dtb] - pass dtb file
- Fix timer issues
- Fix issues with UART and console
- Implement proper TLB cache
- Improve speed
- Implement f and d RISC-V extensions