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board_enable.c
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board_enable.c
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/*
* This file is part of the flashrom project.
*
* Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
* Copyright (C) 2007 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* Contains the board specific flash enables.
*/
#include <strings.h>
#include <string.h>
#include <stdlib.h>
#include "flash.h"
#include "programmer.h"
#include "hwaccess.h"
#if defined(__i386__) || defined(__x86_64__)
/*
* Helper functions for many Winbond Super I/Os of the W836xx range.
*/
/* Enter extended functions */
void w836xx_ext_enter(uint16_t port)
{
OUTB(0x87, port);
OUTB(0x87, port);
}
/* Leave extended functions */
void w836xx_ext_leave(uint16_t port)
{
OUTB(0xAA, port);
}
/* Generic Super I/O helper functions */
uint8_t sio_read(uint16_t port, uint8_t reg)
{
OUTB(reg, port);
return INB(port + 1);
}
void sio_write(uint16_t port, uint8_t reg, uint8_t data)
{
OUTB(reg, port);
OUTB(data, port + 1);
}
void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
{
uint8_t tmp;
OUTB(reg, port);
tmp = INB(port + 1) & ~mask;
OUTB(tmp | (data & mask), port + 1);
}
/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
{
uint8_t tmp;
OUTB(reg, port);
tmp = INB(port + 1) & ~mask;
OUTB(reg, port);
OUTB(tmp | (data & mask), port + 1);
}
/* Not used yet. */
#if 0
static int enable_flash_decode_superio(void)
{
int ret;
uint8_t tmp;
switch (superio.vendor) {
case SUPERIO_VENDOR_NONE:
ret = -1;
break;
case SUPERIO_VENDOR_ITE:
enter_conf_mode_ite(superio.port);
/* Enable flash mapping. Works for most old ITE style Super I/O. */
tmp = sio_read(superio.port, 0x24);
tmp |= 0xfc;
sio_write(superio.port, 0x24, tmp);
exit_conf_mode_ite(superio.port);
ret = 0;
break;
default:
msg_pdbg("Unhandled Super I/O type!\n");
ret = -1;
break;
}
return ret;
}
#endif
/*
* SMSC FDC37B787: Raise GPIO50
*/
static int fdc37b787_gpio50_raise(uint16_t port)
{
uint8_t id, val;
OUTB(0x55, port); /* enter conf mode */
id = sio_read(port, 0x20);
if (id != 0x44) {
msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
OUTB(0xAA, port); /* leave conf mode */
return -1;
}
sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
val = sio_read(port, 0xC8); /* GP50 */
if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
{
msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
OUTB(0xAA, port);
return -1;
}
sio_mask(port, 0xF9, 0x01, 0x01);
OUTB(0xAA, port); /* Leave conf mode */
return 0;
}
/*
* Suited for:
* - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
*/
static int fdc37b787_gpio50_raise_3f0(void)
{
return fdc37b787_gpio50_raise(0x3f0);
}
struct winbond_mux {
uint8_t reg; /* 0 if the corresponding pin is not muxed */
uint8_t data; /* reg/data/mask may be directly ... */
uint8_t mask; /* ... passed to sio_mask */
};
struct winbond_port {
const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
uint8_t ldn; /* LDN this GPIO register is located in */
uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
the GPIO port */
uint8_t base; /* base register in that LDN for the port */
};
struct winbond_chip {
uint8_t device_id; /* reg 0x20 of the expected w83626x */
uint8_t gpio_port_count;
const struct winbond_port *port;
};
#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
enum winbond_id {
WINBOND_W83627HF_ID = 0x52,
WINBOND_W83627EHF_ID = 0x88,
WINBOND_W83627THF_ID = 0x82,
WINBOND_W83697HF_ID = 0x60,
};
static const struct winbond_mux w83627hf_port2_mux[8] = {
{0x2A, 0x01, 0x01}, /* or MIDI */
{0x2B, 0x80, 0x80}, /* or SPI */
{0x2B, 0x40, 0x40}, /* or SPI */
{0x2B, 0x20, 0x20}, /* or power LED */
{0x2B, 0x10, 0x10}, /* or watchdog */
{0x2B, 0x08, 0x08}, /* or infra red */
{0x2B, 0x04, 0x04}, /* or infra red */
{0x2B, 0x03, 0x03} /* or IRQ1 input */
};
static const struct winbond_port w83627hf[3] = {
UNIMPLEMENTED_PORT,
{w83627hf_port2_mux, 0x08, 0, 0xF0},
UNIMPLEMENTED_PORT,
};
static const struct winbond_mux w83627ehf_port2_mux[8] = {
{0x29, 0x06, 0x02}, /* or MIDI */
{0x29, 0x06, 0x02},
{0x24, 0x02, 0x00}, /* or SPI ROM interface */
{0x24, 0x02, 0x00},
{0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
{0x2A, 0x01, 0x01},
{0x2A, 0x01, 0x01},
{0x2A, 0x01, 0x01},
};
static const struct winbond_port w83627ehf[6] = {
UNIMPLEMENTED_PORT,
{w83627ehf_port2_mux, 0x09, 0, 0xE3},
UNIMPLEMENTED_PORT,
UNIMPLEMENTED_PORT,
UNIMPLEMENTED_PORT,
UNIMPLEMENTED_PORT,
};
static const struct winbond_mux w83627thf_port4_mux[8] = {
{0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
{0x2D, 0x02, 0x02}, /* or resume reset */
{0x2D, 0x04, 0x04}, /* or S3 input */
{0x2D, 0x08, 0x08}, /* or PSON# */
{0x2D, 0x10, 0x10}, /* or PWROK */
{0x2D, 0x20, 0x20}, /* or suspend LED */
{0x2D, 0x40, 0x40}, /* or panel switch input */
{0x2D, 0x80, 0x80}, /* or panel switch output */
};
static const struct winbond_port w83627thf[5] = {
UNIMPLEMENTED_PORT, /* GPIO1 */
UNIMPLEMENTED_PORT, /* GPIO2 */
UNIMPLEMENTED_PORT, /* GPIO3 */
{w83627thf_port4_mux, 0x09, 1, 0xF4},
UNIMPLEMENTED_PORT, /* GPIO5 */
};
static const struct winbond_chip winbond_chips[] = {
{WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
{WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
{WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
};
#define WINBOND_SUPERIO_PORT1 0x2e
#define WINBOND_SUPERIO_PORT2 0x4e
/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
* the simple device ID in the normal configuration registers.
* Note: This function expects to be called while the Super I/O is in config mode.
*/
static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
{
uint16_t hwmport;
uint16_t hwm_vendorid;
uint8_t hwm_deviceid;
sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
return 0;
}
/* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
hwmport = sio_read(sio_port, 0x60) << 8;
hwmport |= sio_read(sio_port, 0x61);
/* HWM address register = HWM base address + 5. */
hwmport += 5;
msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
/* FIXME: This busy check should happen before each HWM access. */
if (INB(hwmport) & 0x80) {
msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
return 0;
}
/* Set HBACS=1. */
sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
/* Read upper byte of vendor ID. */
hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
/* Set HBACS=0. */
sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
/* Read lower byte of vendor ID. */
hwm_vendorid |= sio_read(hwmport, 0x4f);
if (hwm_vendorid != 0x5ca3) {
msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
hwm_vendorid);
return 0;
}
/* Set Bank=0. */
sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
/* Read "chip" ID. We call this one the device ID. */
hwm_deviceid = sio_read(hwmport, 0x58);
return hwm_deviceid;
}
void probe_superio_winbond(void)
{
struct superio s = {0};
uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
uint16_t *i = winbond_ports;
uint8_t model;
uint8_t tmp;
s.vendor = SUPERIO_VENDOR_WINBOND;
for (; *i; i++) {
s.port = *i;
/* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
w836xx_ext_enter(s.port);
model = sio_read(s.port, 0x20);
/* No response, no point leaving the config mode. */
if (model == 0xff)
continue;
/* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
w836xx_ext_leave(s.port);
if (model == sio_read(s.port, 0x20)) {
msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
"leave config mode had no effect.\n");
if (model == 0x87) {
/* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
* but they want the ITE exit sequence. Handle them here.
*/
tmp = sio_read(s.port, 0x21);
switch (tmp) {
case 0x07:
case 0x10:
s.vendor = SUPERIO_VENDOR_ITE;
s.model = (0x87 << 8) | tmp ;
msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
"0x%x\n", s.model, s.port);
register_superio(s);
/* Exit ITE config mode. */
exit_conf_mode_ite(s.port);
/* Restore vendor for next loop iteration. */
s.vendor = SUPERIO_VENDOR_WINBOND;
continue;
}
}
msg_pdbg("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
continue;
}
/* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
w836xx_ext_enter(s.port);
s.model = sio_read(s.port, 0x20);
switch (s.model) {
case WINBOND_W83627HF_ID:
case WINBOND_W83627EHF_ID:
case WINBOND_W83627THF_ID:
msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
register_superio(s);
break;
case WINBOND_W83697HF_ID:
/* This code is extremely paranoid. */
tmp = sio_read(s.port, 0x26) & 0x40;
if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
"0x%02x at port 0x%04x\n", s.model, s.port);
break;
}
tmp = w836xx_deviceid_hwmon(s.port);
/* FIXME: This might be too paranoid... */
if (!tmp) {
msg_pdbg("Probably not a Winbond Super I/O\n");
break;
}
if (tmp != s.model) {
msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
"got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
break;
}
msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
register_superio(s);
break;
}
w836xx_ext_leave(s.port);
}
return;
}
static const struct winbond_chip *winbond_superio_chipdef(void)
{
int i, j;
for (i = 0; i < superio_count; i++) {
if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
continue;
for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
if (winbond_chips[j].device_id == superios[i].model)
return &winbond_chips[j];
}
return NULL;
}
/*
* The chipid parameter goes away as soon as we have Super I/O matching in the
* board enable table. The call to winbond_superio_detect() goes away as
* soon as we have generic Super I/O detection code.
*/
static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
int pin, int raise)
{
const struct winbond_chip *chip = NULL;
const struct winbond_port *gpio;
int port = pin / 10;
int bit = pin % 10;
chip = winbond_superio_chipdef();
if (!chip) {
msg_perr("\nERROR: No supported Winbond Super I/O found\n");
return -1;
}
if (chip->device_id != chipid) {
msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
"expected %x\n", chip->device_id, chipid);
return -1;
}
if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
pin);
return -1;
}
gpio = &chip->port[port - 1];
if (gpio->ldn == 0) {
msg_perr("\nERROR: GPIO%d is not supported yet on this"
" winbond chip\n", port);
return -1;
}
w836xx_ext_enter(base);
/* Select logical device. */
sio_write(base, 0x07, gpio->ldn);
/* Activate logical device. */
sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
/* Select GPIO function of that pin. */
if (gpio->mux && gpio->mux[bit].reg)
sio_mask(base, gpio->mux[bit].reg,
gpio->mux[bit].data, gpio->mux[bit].mask);
sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
w836xx_ext_leave(base);
return 0;
}
/*
* Winbond W83627HF: Raise GPIO24.
*
* Suited for:
* - Agami Aruma
* - IWILL DK8-HTX
*/
static int w83627hf_gpio24_raise_2e(void)
{
return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
}
/*
* Winbond W83627HF: Raise GPIO25.
*
* Suited for:
* - MSI MS-6577
*/
static int w83627hf_gpio25_raise_2e(void)
{
return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
}
/*
* Winbond W83627EHF: Raise GPIO22.
*
* Suited for:
* - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
*/
static int w83627ehf_gpio22_raise_2e(void)
{
return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
}
/*
* Winbond W83627THF: Raise GPIO 44.
*
* Suited for:
* - MSI K8T Neo2-F V2.0
*/
static int w83627thf_gpio44_raise_2e(void)
{
return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
}
/*
* Winbond W83627THF: Raise GPIO 44.
*
* Suited for:
* - MSI K8N Neo3
*/
static int w83627thf_gpio44_raise_4e(void)
{
return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
}
/*
* Enable MEMW# and set ROM size to max.
* Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
*/
static void w836xx_memw_enable(uint16_t port)
{
w836xx_ext_enter(port);
if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
/* Enable MEMW# and set ROM size select to max. (4M). */
sio_mask(port, 0x24, 0x28, 0x28);
}
w836xx_ext_leave(port);
}
/**
* Enable MEMW# and set ROM size to max.
* Supported chips:
* W83697HF/F/HG, W83697SF/UF/UG
*/
void w83697xx_memw_enable(uint16_t port)
{
w836xx_ext_enter(port);
if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
/* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
/* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
/* These bits are reserved on W83697HF/F/HG */
/* Shouldn't be needed though. */
/* CR28 Bit3 must be set to 1 to enable flash access to */
/* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
/* This bit is reserved on W83697HF/F/HG which default to 0 */
sio_mask(port, 0x28, 0x08, 0x08);
/* Enable MEMW# and set ROM size select to max. (4M)*/
sio_mask(port, 0x24, 0x28, 0x38);
} else {
msg_pwarn("Warning: Flash interface in use by GPIO!\n");
}
} else {
msg_pinfo("BIOS ROM is disabled\n");
}
w836xx_ext_leave(port);
}
/*
* Suited for:
* - Biostar M7VIQ: VIA KM266 + VT8235
*/
static int w83697xx_memw_enable_2e(void)
{
w83697xx_memw_enable(0x2E);
return 0;
}
/*
* Suited for:
* - DFI AD77: VIA KT400 + VT8235 + W83697HF
* - EPoX EP-8K5A2: VIA KT333 + VT8235
* - Albatron PM266A Pro: VIA P4M266A + VT8235
* - Shuttle AK31 (all versions): VIA KT266 + VT8233
* - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
* - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
* - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
* - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
* - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
* - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
* - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
*/
static int w836xx_memw_enable_2e(void)
{
w836xx_memw_enable(0x2E);
return 0;
}
/*
* Suited for:
* - Termtek TK-3370 (rev. 2.5b)
*/
static int w836xx_memw_enable_4e(void)
{
w836xx_memw_enable(0x4E);
return 0;
}
/*
* Suited for all boards with ITE IT8705F.
* The SIS950 Super I/O probably requires a similar flash write enable.
*/
int it8705f_write_enable(uint8_t port)
{
uint8_t tmp;
int ret = 0;
enter_conf_mode_ite(port);
tmp = sio_read(port, 0x24);
/* Check if at least one flash segment is enabled. */
if (tmp & 0xf0) {
/* The IT8705F will respond to LPC cycles and translate them. */
internal_buses_supported = BUS_PARALLEL;
/* Flash ROM I/F Writes Enable */
tmp |= 0x04;
msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
if (tmp & 0x02) {
/* The data sheet contradicts itself about max size. */
max_rom_decode.parallel = 1024 * 1024;
msg_pinfo("IT8705F with very unusual settings.\n"
"Please send the output of \"flashrom -V -p internal\" to flashrom@flashrom.org\n"
"with \"IT8705: your board name: flashrom -V\" as the subject to help us finish\n"
"support for your Super I/O. Thanks.\n");
ret = 1;
} else if (tmp & 0x08) {
max_rom_decode.parallel = 512 * 1024;
} else {
max_rom_decode.parallel = 256 * 1024;
}
/* Safety checks. The data sheet is unclear here: Segments 1+3
* overlap, no segment seems to cover top - 1MB to top - 512kB.
* We assume that certain combinations make no sense.
*/
if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
(!(tmp & 0x10)) || /* 128 kB dis */
(!(tmp & 0x40))) { /* 256/512 kB dis */
msg_perr("Inconsistent IT8705F decode size!\n");
ret = 1;
}
if (sio_read(port, 0x25) != 0) {
msg_perr("IT8705F flash data pins disabled!\n");
ret = 1;
}
if (sio_read(port, 0x26) != 0) {
msg_perr("IT8705F flash address pins 0-7 disabled!\n");
ret = 1;
}
if (sio_read(port, 0x27) != 0) {
msg_perr("IT8705F flash address pins 8-15 disabled!\n");
ret = 1;
}
if ((sio_read(port, 0x29) & 0x10) != 0) {
msg_perr("IT8705F flash write enable pin disabled!\n");
ret = 1;
}
if ((sio_read(port, 0x29) & 0x08) != 0) {
msg_perr("IT8705F flash chip select pin disabled!\n");
ret = 1;
}
if ((sio_read(port, 0x29) & 0x04) != 0) {
msg_perr("IT8705F flash read strobe pin disabled!\n");
ret = 1;
}
if ((sio_read(port, 0x29) & 0x03) != 0) {
msg_perr("IT8705F flash address pins 16-17 disabled!\n");
/* Not really an error if you use flash chips smaller
* than 256 kByte, but such a configuration is unlikely.
*/
ret = 1;
}
msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
max_rom_decode.parallel);
if (ret) {
msg_pinfo("Not enabling IT8705F flash write.\n");
} else {
sio_write(port, 0x24, tmp);
}
} else {
msg_pdbg("No IT8705F flash segment enabled.\n");
ret = 0;
}
exit_conf_mode_ite(port);
return ret;
}
/*
* The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
* It uses the Winbond command sequence to enter extended configuration
* mode and the ITE sequence to exit.
*
* Registers seems similar to the ones on ITE IT8710F.
*/
static int it8707f_write_enable(uint8_t port)
{
uint8_t tmp;
w836xx_ext_enter(port);
/* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
tmp = sio_read(port, 0x23);
tmp |= (1 << 3);
sio_write(port, 0x23, tmp);
/* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
tmp = sio_read(port, 0x24);
tmp |= (1 << 2) | (1 << 3);
sio_write(port, 0x24, tmp);
/* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
tmp = sio_read(port, 0x23);
tmp &= ~(1 << 3);
sio_write(port, 0x23, tmp);
exit_conf_mode_ite(port);
return 0;
}
/*
* Suited for:
* - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
*/
static int it8707f_write_enable_2e(void)
{
return it8707f_write_enable(0x2e);
}
#define PC87360_ID 0xE1
#define PC87364_ID 0xE4
static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
{
static const int bankbase[] = {0, 4, 8, 10, 12};
int gpio_bank = gpio / 8;
int gpio_pin = gpio % 8;
uint16_t baseport;
uint8_t id, val;
if (gpio_bank > 4) {
msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
return -1;
}
id = sio_read(0x2E, 0x20);
if (id != chipid) {
msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
id, chipid);
return -1;
}
sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
msg_perr("PC87360: invalid GPIO base address %04x\n",
baseport);
return -1;
}
sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
val = INB(baseport + bankbase[gpio_bank]);
if (raise)
val |= 1 << gpio_pin;
else
val &= ~(1 << gpio_pin);
OUTB(val, baseport + bankbase[gpio_bank]);
return 0;
}
/*
* VIA VT823x: Set one of the GPIO pins.
*/
static int via_vt823x_gpio_set(uint8_t gpio, int raise)
{
struct pci_dev *dev;
uint16_t base;
uint8_t val, bit, offset;
dev = pci_dev_find_vendorclass(0x1106, 0x0601);
switch (dev->device_id) {
case 0x3177: /* VT8235 */
case 0x3227: /* VT8237/VT8237R */
case 0x3337: /* VT8237A */
break;
default:
msg_perr("\nERROR: VT823x ISA bridge not found.\n");
return -1;
}
if ((gpio >= 12) && (gpio <= 15)) {
/* GPIO12-15 -> output */
val = pci_read_byte(dev, 0xE4);
val |= 0x10;
pci_write_byte(dev, 0xE4, val);
} else if (gpio == 9) {
/* GPIO9 -> Output */
val = pci_read_byte(dev, 0xE4);
val |= 0x20;
pci_write_byte(dev, 0xE4, val);
} else if (gpio == 5) {
val = pci_read_byte(dev, 0xE4);
val |= 0x01;
pci_write_byte(dev, 0xE4, val);
} else {
msg_perr("\nERROR: "
"VT823x GPIO%02d is not implemented.\n", gpio);
return -1;
}
/* We need the I/O Base Address for this board's flash enable. */
base = pci_read_word(dev, 0x88) & 0xff80;
offset = 0x4C + gpio / 8;
bit = 0x01 << (gpio % 8);
val = INB(base + offset);
if (raise)
val |= bit;
else
val &= ~bit;
OUTB(val, base + offset);
return 0;
}
/*
* Suited for:
* - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
*/
static int via_vt823x_gpio5_raise(void)
{
/* On M2V-MX: GPO5 is connected to WP# and TBL#. */
return via_vt823x_gpio_set(5, 1);
}
/*
* Suited for:
* - VIA EPIA EK & N & NL
*/
static int via_vt823x_gpio9_raise(void)
{
return via_vt823x_gpio_set(9, 1);
}
/*
* Suited for:
* - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
*
* We don't need to do this for EPIA M when using coreboot, GPIO15 is never
* lowered there.
*/
static int via_vt823x_gpio15_raise(void)
{
return via_vt823x_gpio_set(15, 1);
}
/*
* Winbond W83697HF Super I/O + VIA VT8235 southbridge
*
* Suited for:
* - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
* - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
*/
static int board_msi_kt4v(void)
{
int ret;
ret = via_vt823x_gpio_set(12, 1);
w836xx_memw_enable(0x2E);
return ret;
}
/*
* Suited for:
* - ASUS P5A
*
* This is rather nasty code, but there's no way to do this cleanly.
* We're basically talking to some unknown device on SMBus, my guess
* is that it is the Winbond W83781D that lives near the DIP BIOS.
*/
static int board_asus_p5a(void)
{
uint8_t tmp;
int i;
#define ASUSP5A_LOOP 5000
OUTB(0x00, 0xE807);
OUTB(0xEF, 0xE803);
OUTB(0xFF, 0xE800);
for (i = 0; i < ASUSP5A_LOOP; i++) {
OUTB(0xE1, 0xFF);
if (INB(0xE800) & 0x04)
break;
}
if (i == ASUSP5A_LOOP) {
msg_perr("Unable to contact device.\n");
return -1;
}
OUTB(0x20, 0xE801);
OUTB(0x20, 0xE1);
OUTB(0xFF, 0xE802);
for (i = 0; i < ASUSP5A_LOOP; i++) {
tmp = INB(0xE800);
if (tmp & 0x70)
break;
}
if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
msg_perr("Failed to read device.\n");
return -1;
}
tmp = INB(0xE804);
tmp &= ~0x02;
OUTB(0x00, 0xE807);
OUTB(0xEE, 0xE803);
OUTB(tmp, 0xE804);
OUTB(0xFF, 0xE800);
OUTB(0xE1, 0xFF);
OUTB(0x20, 0xE801);
OUTB(0x20, 0xE1);
OUTB(0xFF, 0xE802);
for (i = 0; i < ASUSP5A_LOOP; i++) {
tmp = INB(0xE800);
if (tmp & 0x70)
break;
}
if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
msg_perr("Failed to write to device.\n");
return -1;
}
return 0;
}
/*
* Set GPIO lines in the Broadcom HT-1000 southbridge.
*
* It's not a Super I/O but it uses the same index/data port method.
*/
static int board_hp_dl145_g3_enable(void)
{
/* GPIO 0 reg from PM regs */
/* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
sio_mask(0xcd6, 0x44, 0x24, 0x24);
return 0;
}
/*
* Set GPIO lines in the Broadcom HT-1000 southbridge.
*
* It's not a Super I/O but it uses the same index/data port method.
*/
static int board_hp_dl165_g6_enable(void)
{
/* Variant of DL145, with slightly different pin placement. */
sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
return 0;
}
static int board_ibm_x3455(void)
{
/* Raise GPIO13. */
sio_mask(0xcd6, 0x45, 0x20, 0x20);
return 0;
}
/*
* Suited for:
* - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
*/
static int board_ecs_geforce6100sm_m(void)
{
struct pci_dev *dev;
uint32_t tmp;
dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
if (!dev) {
msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");