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Add strategy to remove -retime flag from Vivado #34

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Mar 2, 2021
Merged

Add strategy to remove -retime flag from Vivado #34

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2 changes: 1 addition & 1 deletion hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl
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Expand Up @@ -117,7 +117,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes

update_compile_order -fileset sources_1
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive -retiming]
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]

set failval [catch {exec grep "FAIL" failfast.csv}]
if { $failval==0 } {
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2 changes: 1 addition & 1 deletion hdk/common/shell_v04261818/build/scripts/strategy_BASIC.tcl
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Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-keep_equivalent_registers $synth_uram_option"
set synth_options "-keep_equivalent_registers $synth_uram_option -retiming"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
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2 changes: 1 addition & 1 deletion hdk/common/shell_v04261818/build/scripts/strategy_CONGESTION.tcl
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Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-no_lc -shreg_min_size 10 -control_set_opt_threshold 16 $synth_uram_option"
set synth_options "-no_lc -shreg_min_size 10 -control_set_opt_threshold 16 $synth_uram_option -retiming"
set synth_directive "AlternateRoutability"

#Set psip to 1 to enable Physical Synthesis in Placer
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2 changes: 1 addition & 1 deletion hdk/common/shell_v04261818/build/scripts/strategy_DEFAULT.tcl
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Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option"
set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option -retiming"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
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2 changes: 1 addition & 1 deletion hdk/common/shell_v04261818/build/scripts/strategy_EXPLORE.tcl
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Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option"
set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option -retiming"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
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58 changes: 58 additions & 0 deletions hdk/common/shell_v04261818/build/scripts/strategy_NORETIMING.tcl
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@@ -0,0 +1,58 @@
# Amazon FPGA Hardware Development Kit
#
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
#
# Licensed under the Amazon Software License (the "License"). You may not use
# this file except in compliance with the License. A copy of the License is
# located at
#
# http://aws.amazon.com/asl/
#
# or in the "license" file accompanying this file. This file is distributed on
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
# implied. See the License for the specific language governing permissions and
# limitations under the License.

source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
set psip 0

set link 1

set opt 1
set opt_options ""
set opt_directive "Explore"
set opt_preHookTcl "$HDK_SHELL_DIR/build/scripts/check_uram.tcl"
set opt_postHookTcl "$HDK_SHELL_DIR/build/scripts/apply_debug_constraints.tcl"

set place 1
set place_options ""
set place_directive "ExtraNetDelay_high"
set place_preHookTcl ""
set place_postHookTcl ""

set phys_opt 1
set phys_options ""
set phys_directive ""
set phys_directive "AggressiveExplore"
set phys_preHookTcl ""
set phys_postHookTcl ""

set route 1
set route_options "-tns_cleanup"
set route_directive "Explore"
set route_preHookTcl ""
set route_postHookTcl ""

set route_phys_opt 1
set post_phys_options ""
set post_phys_directive "AggressiveExplore"
set post_phys_preHookTcl ""
set post_phys_postHookTcl ""


2 changes: 1 addition & 1 deletion hdk/common/shell_v04261818/build/scripts/strategy_TIMING.tcl
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Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option"
set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option -retiming"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
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