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Fixes for Chisel 3.6 support #1395

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merged 4 commits into from Jan 20, 2023
Merged

Fixes for Chisel 3.6 support #1395

merged 4 commits into from Jan 20, 2023

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sifive-benjamin-morse
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Related PRs / Issues

UI / API Impact

These are required to allow Firesim to upgrade to Chisel version 3.6

Verilog / AGFI Compatibility

no changes

Contributor Checklist

  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you add Scaladoc/docstring/doxygen to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous prints/debugging code?
  • Did you state the UI / API impact?
  • Did you specify the Verilog / AGFI compatibility impact?
  • If applicable, did you regenerate and publicly share default AGFIs?
  • If applicable, did you apply the ci:fpga-deploy label?
  • If applicable, did you apply the Please Backport label?

Reviewer Checklist (only modified by reviewer)

Note: to run CI on PRs from forks, comment @Mergifyio copy main and manage the change from the new PR.

  • Is the title suitable for inclusion in the changelog and does the PR have a changelog:<topic> label?
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@sifive-benjamin-morse sifive-benjamin-morse added the changelog:fixed Put PR title in 'Fixed' section of changelog label Jan 20, 2023
@@ -20,6 +15,11 @@ class AsyncResetReg extends chisel3.Module {

// Transform RocketChip's async reset to sync reset
object AsyncResetRegPass extends firrtl.Transform {
import firrtl._
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This is such a weird change, but i approved it before so, lol

@davidbiancolin
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Context for Berkeley is that these are fixes that should make the codebase compatible with 3.6 (which is what we use at SiFive). A bump to 3.6 itself is not compulsory.

@sifive-benjamin-morse sifive-benjamin-morse merged commit ae9ea90 into main Jan 20, 2023
@sifive-benjamin-morse sifive-benjamin-morse deleted the bmorse/chisel-3.6 branch January 20, 2023 22:01
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3 participants